• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 추계종합학술대회 논문 초록집
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• pp.406-406
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• 2004

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.25-33
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• 2007

본 논문에서는 높은 dynamic range(DR)를 얻을 수 있는 단일-비트 4차 델타-시그마 모듈레이터를 제시하였으며, 이를 구현하였다. 본 모듈레이터에 사용된 루프 필터의 구조는 피드백 패스와 피드포워드 패스를 혼합하여 사용한 구조이며, 스위치-커패시터(switched-capacitor) 방식으로 구현되었다. 측정 결과로는 20kHz의 기저대역(base band)에서 3.2MHz의 클록을 사용하였을 때 최대 99dB의 DR을 얻었다. 본 모듈레이터는 $0.18{\mu}m$ standard CMOS 공정으로 만들어졌다.

• 한국정밀공학회지
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• 제19권3호
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• pp.33-38
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• 2002

To establish the national standard of capacitance, four main electrodes of the cross capacitor which were evaluated to linearity and roundness less the $\pm 1 \mu m$ respectively have to be adjusted symmetrically in an inner cylinder. Four LM shafts with diameter of 5 mm were installed between main electrodes of the cross capacitor, and the electrodes were adjusted, as the first step, by means of the measured capacitance. In the second step, the symmetrical adjustment up to $\pm 1.2\mu m$ was performed by using a ball sensor, ball-type movable sensor, non-contacting capacitive sensor and upper guard sensor which were developed in this project.

• 센서학회지
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• 제25권5호
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• pp.326-332
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• 2016

A novel CMOS temperature sensor with binary output is implemented by using fully differential switched-capacitor circuits for resistorless implementation of the temperature sensor core. Temperature sensing is based on the temperature characteristics of the pn diodes implemented by substrate pnp transistors fabricated using standard CMOS processes. The binary outputs are generated by using the charge-balance principle that eliminates the division operation of the PTAT voltage by the bandgap reference voltage. The chip was designed in a MagnaChip $0.35-{\mu}m$ CMOS process, and the designed circuit was verified using Spectre circuit simulations. The verified circuit was laid out in an area of $950{\mu}m{\times}557 {\mu}m$ and is currently under fabrication.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• 한국정보통신학회논문지
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• 제16권5호
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• pp.989-998
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• 2012

본 논문에서는 매우 작은 절대 값을 갖는 펨토 패럿 단위의 커패시턴스를 측정 할 수 있는 비율형 커패시턴스 측정 회로를 제안하였다. 제안한 측정 회로는 스위치 커패시터 적분기와 비교기 그리고 스위치를 제어하는 논리 회로와 카운터로 구성되어 있으며, 측정하고자 하는 커패시턴스와 이미 값이 알려진 온-칩 커패시터간의 비율을 측정하고 그 값을 디지털 신호로 출력한다. 그리고 이 비율 값을 통해 오차가 상당부분 제거된 펨토 패럿 단위의 커패시턴스를 구해낼 수 있다. 제안한 커패시턴스 측정 회로는 표준 CMOS $0.18{\mu}m$ 공정을 사용하여 설계되었으며, HSpice 시뮬레이션에서 5fF 이하의 아주 작은 커패시턴스를 오차율 ${\pm}0.3%$ 이내에서 측정이 가능함을 보였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.906-909
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• 2006

본 논문은 저 전압 및 저 왜곡 스위치형 커패시터 (switched-capacitor, SC)를 적용한 새로운 형태의 몸체효과 보상형 스위치 구조를 제안한다 제안된 회로는 저 전압 SC 회로를 위해서 rail-to-rail 스위칭을 허용하며 기존의 부트스트랩된 회로 (19dB) 보다 더 우수한 총 고조파 왜곡을 가진다. 설계된 2-1 캐스케이드 시그마 델타 변조기는 통신 송수신시스템내의 오디오 코덱을 위한 고해상도 아날로그-디지털변환을 수행한다. 1단 폴드형 캐스코드 연산증폭기 및 2-1 캐스케이드 시그마 델타 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었으며, 2.7V에서 동작한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전기물성,응용부문
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• pp.62-64
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• 2001

In this paper, we present the fabrication and performance of tunable capacitors with various structural geometry of plates. Experimental devices have been fabricated using Cu-electroplating techniques and standard MEMS techniques. In particular, the thickness of electroplated Cu is designed below $0.5{\mu}m$ for lower actuation voltage. The fabricated tunable capacitors has been tested from $OV{\sim}42V$ and achieves a tuning ratio of $46%{\sim}64.2%$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.16-18
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• 2008

Several methods are proposed in the literature for losses segregation of single phase induction motor. Generally we could divide two methods for experimental determination of losses segregation for single phase induction motor. The one is relatively complicated method based on Parameter estimation of single phase induction motor. The other is simple method based on IEEE Standard 114. Segregation of losses in single phase induction motor is more complicated than that in three phase induction motor, because of the backward magnetic field component in the motor and multiplicity of different single phase type. In this paper, therefore, we studied losses segregation of capacitor-run single phase induction motor.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.283-288
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• 2004

We have fabricated MIM capacitors for MMIC applications, with capacitances as high as 600pF/$\textrm{mm}^2$ and excellent electrical properties of the insulator layer. Silicon nitride thin film is the desirable material for MMIC capacitor fabrication. Standard MIM capacitance in MMIC is 300pF/$\textrm{mm}^2$ with an insulator layer thickness of more than 2000$\AA$. However, capacitors with thin insulator layers have breakdown voltages as low as 20V. We have deposited insulator layers by PECVD in our MIM structure with an air bridge between the top metal and the contact pad. The PECVD process was optimized for fabricating the desired capacitors to be used in MMIC. Silicon nitride(Si$_{x}$N$_{y}$) thin films of about 1000$\AA$ thick show capacitances of about 600pF/$\textrm{mm}^2$, and breakdown voltages above 70V at 100nA.A.A.