• Title/Summary/Keyword: Stack Voltage

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Study on the Structural Stability and Charge Trapping Properties of High-k HfO2 and HFO2/Al2O3/HfO2 Stacks (High-k HfO2와 HfO2/Al2O3/HfO2 적층막의 구조 안정성 및 전하 트랩핑 특성 연구)

  • Ahn, Young-Soo;Huh, Min-Young;Kang, Hae-Yoon;Sohn, Hyunchul
    • Korean Journal of Metals and Materials
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    • v.48 no.3
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    • pp.256-261
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    • 2010
  • In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

Development of DC/DC Converters and Actual Vehicle Simulation Experiment for 150 kW Class Fuel-cell Electric Vehicle (150kW급 수소연료전지 차량용 DC/DC 컨버터 개발 및 실차모사 실험)

  • Kim, Sun-Ju;Jeong, Hyeonju;Choi, Sewan;Cho, Jun-Ho;Jeon, Yujong;Park, Jun-Sung;Yoon, Hye-Sung
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.1
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    • pp.26-32
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    • 2022
  • This paper proposes a power system that includes a 120k W fuel cell DC-DC converter (FDC) and 30 kW bidirectional DC-DC converter (BHDC) for a 150 kW fuel-cell vehicle. With a high DC link voltage of 800 V, the efficiency and power density of the power electronic components are improved. Through the modular design of FDC and BHDC, electric components are shared, resulting in reduced mass production costs. The switching frequency of 30 kHz of full SiC devices and optimal design of coupled inductor reduce the volume, achieving a power density of 8.3 kW/L. Furthermore, a synergetic operation strategy using variable limiter control of FDC and BHDC was proposed to efficiently operate the fuel cell vehicle considering the fuel cell stack efficiency according to the load. Finally, the performance of the prototype was verified by Highway Fuel Economy Driving Schedule testing, EMI test, and the linked operation between FDC and BHDC. The full load efficiencies of the FDC and BHDC prototypes are 98.47% and 98.74%, respectively.

Effect of Current Density and Electroosmotic Phenomena on the Desalination Performance of the Electrodialysis Process (전류밀도와 전기삼투 현상이 전기투석 공정의 탈염성능에 미치는 영향)

  • Eun-Seo Cheon;Jae-Hwan Choi
    • Applied Chemistry for Engineering
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    • v.34 no.3
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    • pp.272-278
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    • 2023
  • In this study, we analyzed the effects of current density and electroosmotic phenomena on the desalination performance of electrodialysis (ED). We conducted ED experiments under constant voltage conditions, changing the concentration of the concentrate solution from 10 to 200 g/L. During the ED operation, we measured the current density and charge supplied to the stack, the concentration of the diluted and concentrated solutions, and the amount of water transported by electroosmosis to analyze desalination performance. As the concentration of the concentrated solution increased, the selectivity of the ion exchange membrane decreased, resulting in a decrease in current efficiency. Moreover, the current efficiency was found to be influenced by the current density supplied. When the current density exceeded 15 mA/cm2, back diffusion of ions was suppressed, leading to an increase in current efficiency. We also investigated the specific water transport by electroosmosis during the ED operation. We found that the amount of water transported increased proportionally to the concentration ratio of the concentrated and diluted solutions. When the concentration ratio exceeded 100, the specific water transport rapidly increased due to osmotic pressure, making it challenging to obtain a concentrated solution greater than 200 g/L.

Electrooptic Modulator with InAs Quantum Dots (InAs/InGaAs 양자점을 이용한 전계광학변조기)

  • Ok, Seong-Hae;Moon, Yon-Tae;Choi, Young-Wan;Son, Chang-Wan;Lee, Seok;Woo, Deok-Ha;Byun, Young-Tae;Jhon, Young-Min;Kim, Sun-Ho;Yi, Jong-Chang;Oh, Jae-Eung
    • Korean Journal of Optics and Photonics
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    • v.17 no.3
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    • pp.278-284
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    • 2006
  • We have fabricated and measured electrooptic modulator using coupled stack InAs/InGaAs quantum dots. The height of the quantum dot is 16 nm and quantum dots are stacked including an InGaAs capping layer. The peak wavelength of photoluminescence is 1260 nm at room temperature and 1158 nm at 12 K. The operation characteristics of the quantum dots show high modulation efficiency of electrooptic modulator at 1550 nm compared to that of existing III-V bulk and MQW type semiconductor. The measured switching voltage ($V\pi$) is 540 and 600 mV, for TE mode and TM mode, respectively. From the results, the modulation efficiency can be determined as 333.3 and $300^{\circ}/V{\cdot}mm$ for TE and TM modes. The results reported here may lead to the design and fabrication of a novel electrooptic modulator with low switching voltage and high efficiency.

A Study on Improved Open-Circuit Voltage Characteristics Through Bi-Layer Structure in Heterojunction Solar Cells (이종접합 태양전지에서의 Bi-Layer 구조를 통한 향상된 개방전압특성에 대한 고찰)

  • Kim, Hongrae;Jeong, Sungjin;Cho, Jaewoong;Kim, Sungheon;Han, Seungyong;Dhungel, Suresh Kumar;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.6
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    • pp.603-609
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    • 2022
  • Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I1) and the next one a-SiOx:H(I2) were used, where a-SiOx:H(I2) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I1). Using a-SiOx:H as I2 layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiOx:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiOx:H microstructure can help the carrier transportation through tunneling and thermal emission.

Characteristics of Si Floating Gate Nonvolatile Memory Based on Schottky Barrier Tunneling Transistor (쇼트키 장벽 관통 트랜지스터 구조를 적용한 실리콘 나노점 부유 게이트 비휘발성 메모리 특성)

  • Son, Dae-Ho;Kim, Eun-Kyeom;Kim, Jeong-Ho;Lee, Kyung-Su;Yim, Tae-Kyung;An, Seung-Man;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Kim, Tae-You;Jang, Moon-Gyu;Park, Kyoung-Wan
    • Journal of the Korean Vacuum Society
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    • v.18 no.4
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    • pp.302-309
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    • 2009
  • We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.