• Title/Summary/Keyword: Stability margins

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Application of an Adaptive Autopilot Design and Stability Analysis to an Anti-Ship Missile

  • Han, Kwang-Ho;Sung, Jae-Min;Kim, Byoung-Soo
    • International Journal of Aeronautical and Space Sciences
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    • v.12 no.1
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    • pp.78-83
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    • 2011
  • Traditional autopilot design requires an accurate aerodynamic model and relies on a gain schedule to account for system nonlinearities. This paper presents the control architecture applied to a dynamic model inversion at a single flight condition with an on-line neural network (NN) in order to regulate errors caused by approximate inversion. This eliminates the need for an extensive design process and accurate aerodynamic data. The simulation results using a developed full nonlinear 6 degree of freedom model are presented. This paper also presents the stability evaluation for control systems to which NNs were applied. Although feedback can accommodate uncertainty to meet system performance specifications, uncertainty can also affect the stability of the control system. The importance of robustness has long been recognized and stability margins were developed to quantify it. However, the traditional stability margin techniques based on linear control theory can not be applied to control systems upon which a representative non-linear control method, such as NNs, has been applied. This paper presents an alternative stability margin technique for NNs applied to control systems based on the system responses to an inserted gain multiplier or time delay element.

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

  • Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.184-188
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    • 2014
  • There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

On Control Strategies for BTB Converters for Enhancement of Interface Flow Margins (융통전력 여유 향상을 위한 BTB 컨버터 제어 전략 수립)

  • Ohn, Sung-Min;Song, Hwa-Chang;Jang, Byong-Hoon
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.374-375
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    • 2011
  • This paper presents a method to determine parameters of BTB (back-to-back) converters in terms of the enhancement of interface flow margins. Interface flow margin is by definition a measure of how much active power can be transferred from the external areas to the study area with the fixed load demand, and it is mainly constrained by system voltage stability. BTB converters are controllable equipments with the active power flow through them, and its DC link in fact can divide the AC systems at the location and hence can reduce the fault current level. This paper first cals margin sensitivities at the nose point of F-V curves and formulates an optimization problem to update the BTB parameters to improve the margins. This procedure is repeated performed until the required margin enhancement is achieved.

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On gait control of a quadruped walking robot (사각 보행 로보트의 걸음새 제어에 관한 연구)

  • 임미섭;임준홍
    • 제어로봇시스템학회:학술대회논문집
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    • 1988.10a
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    • pp.113-118
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    • 1988
  • The problem of controlling static gaits of a Quadruped Walking Robot is investigated. A theoretical approach to the gait study is proposed in which the static stability margins for periodic gaits are expressed in terms of the kinematic gait formula. The effects of the stride length to the static stability are analyzed, and the relations between the static stability and the initial body configurations are examined. Extensive computer simulations are performed to verify the analysis results.

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Frequency Response Based Multi-objective Design Tool for PID Controller (PID 제어기의 주파수응답 기반 다목적 설계도구)

  • Jin, Li-Hua;Lim, Yearn-Su;Kim, Young-Chol
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1749-1750
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    • 2008
  • This paper presents a Matlab toolbox for proportional-integral-derivative (PID) controller design. By means of the tool, the complete set of controllers simultaneously satisfying multiple design specifications such as stability and robust stability margins can be obtained directly from the only frequency response data on the plant.

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Analysis of coefficient quantization error effects in digital PID controllers (디지틀 PID제어기에서의 계수양자화 오차 영향분석)

  • 이상정;홍석민;윤기준
    • 제어로봇시스템학회:학술대회논문집
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    • 1989.10a
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    • pp.477-482
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    • 1989
  • In this paper, the effect of coefficient quantization error is analyzed for digital PID controllers. Stability margins are used as peformance criteria, and the statistical wordlength concept is adopted for coefficient wordlength selection. Finally, an illustrative example is given.

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Stability Margin of Finite Wordlength(FWL) Effects in Digital Implementation of Controllers (디지털 제어기 구현시 FWL 영향에 대한 안정도 여유)

  • Kim, Jin-Ho;Choi, Sun-Wook;Kim, Young-Chol
    • Proceedings of the KIEE Conference
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    • 1999.11c
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    • pp.533-536
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    • 1999
  • We consider digital implementation problems of continuous-time controllers. In general, digital controllers use fixed point representation of number and of finite word length(FWL). Under these conditions, this paper investigates the closed-loop stability caused by three design constraints; (i) finite precision representation of the controller parameters, (ii) realization forms such as direct form, cascade form, and parallel form, and (iii) sampling time. We calculate the coefficient stability margins of both predesigned controllers and controller to be implemented. This method can be applied to determine the word length, realization structure, and sampling time so that remains the stability.

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Stability analysis of fuzzy logic controller using the concept of sector bound nonlinearity (제한된 부채꼴에서의 비선형 개념을 이용한 퍼지 논리제어기의 안정성 해석)

  • 김인익;박상배;이균경
    • 제어로봇시스템학회:학술대회논문집
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    • 1991.10a
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    • pp.573-578
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    • 1991
  • A stability analysis technique has been proposed for linear SISO system associated with fuzzy logic controller. An analysis technique using the concept of well-known sector bound nonlinearity and its graphical interpretation, i.e., the circle criterion, is presented. Thus the use of classical Nyquist locus and the BODE diagram is brought into the picture. The aim of this present note is to represent a graphical approach based on sector bound nonlinearity and circle criterion for assessing the performance(degree of stability) of the linear SISO system associated with fuzzy logic controller. The degree of stability of the system is defined in terms of its gain and phase margins as defined in Section 3.

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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

  • Yamauchi, Hiroyuki
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.118-129
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    • 2010
  • A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.