• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.128-136
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• 2001

This paper evaluates the performance of an optic link in a frequency conversion based fiber-radio system. The proposed link structure simplifies a BS(base station) via making the MMW(millimeter wave) optical pilot tone generated in the CS(control station) be used in the uplink as well as in the downlink. To acquire the optical pilot tone, an EOM(electro-optic modulator) in the CS is biased in three different ways, i.e., MAB(maximum bias), MIB(minimum bias), QB(quadrature bias). We, depending on the biasing of the EOM, evaluate the link performances in two cases; one is for constant laser source power and the other for constant received DC optical power at a PD(photo detector). Based on the simulation results on the downlink CNR and the uplink SFDR(spurious free dynamic range), we finally deduce the effective EOM biasing for each case.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.580-587
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• 2003

In this paper, we introduce a novel model to analyze the linearity of a TW-EAM (traveling-wave electroabsorption modulator). The device length, microwave loss (ML), and internal reflection (IR) due to impedance mismatch have effect on the linearity of a TW-EAM. The longer devices have characteristics of lower biases with minimum IMDS (intermodulation distortions). ML decreases the output power as well as the IMD value. Internal reflection has different nonlinear characteristics according to the wavelength of the input frequency and the device length. There is little change in SFDR (spurious-free dynamic range) due to ML or IR. As a result, for a 50 GHz band RF-optical communication system, a 0.8 mm-long TW-EAM with the lowest ML would have better properties by using n, which is caused by impedance, mismatch at the output port.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.3
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• pp.371-375
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• 2014

In this paper, we compared the performances of the Right Handed Transmission Line (RHTL) and the Left Handed Transmission Line (LHTL) phase shifters as a frequency translator. Unlike other phase shifters, both phase shifters show a $0^{\circ}-360^{\circ}$ phase variation for a broadband frequency and compact in size which are ideal to use as a frequency translator. For the performance comparison, we fabricated both a RHTL and a LHTL phase shifter to cover 1.5 GHz - 2.4 GHz range with the whole $360^{\circ}$ phase variation. For the frequency range, a LHTL based frequency translator showed a much better performance whose Spurious Free Dynamic Range (SFDR) is 4dB - 17dB higher than the RHTL based frequency translator when the sawtooth modulation freqncy is 11 kHz. This is due to the linear phase-voltage variation of LHTL phase shifter. Furthermore, the LHTL phase shifter shows a less insertion loss and a insertion loss variation than the RHTL phase shifter. Overall, the LHTL based frequency translator outperformed RHTL based freqency translator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.1-9
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• 2007

Linearity is the one of the most important features for analog-optic transmission system. In our research, the available bandwidth for the feed-forward compensation circuit is enhanced by using a 180 hybrid coupler in the circuit. The bandwidth having the decreased 3rd-order intermodulation distortion(IMD3) over 10 dB is extended over 200 MHz with the center frequency of 1.6 GHz. We performed an efficient bandwith measurement for the feed-forward compensation system, which uses the network analyzer instead of the traditional measuring system that uses two RF signal generators and the spectrum analyzer. We identify the usefulness of this method from experimental results. In this study, we used cheap digital-purpose laser diodes for economical aspect, which proves the efficiency of the proposed analog system. The spurious-free dynamic range is improved about 6 dB/Hz.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.