• Korean Journal of Child Studies
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• v.38 no.2
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• pp.107-117
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• 2017

Objective: Whereas some studies have suggested that source monitoring is significantly associated with working memory and inhibitory control, both of which are components of executive functioning, other studies have argued otherwise. The author of this study determined that such contradictory findings are a result of heterogeneity in the assessment methods for source monitoring. Therefore, this study aimed at exploring whether the relationships among source monitoring, working memory, and inhibitory control may be altered depending on the differences of source recall conditions. Methods: Eighty children aged 5-8 years saw interesting activities via two different sources. Their source memories on the activity were assessed subsequently. The children were assigned to either the "continuous" source recall group or "non-continuous" source recall group. Both groups participated in working memory and inhibitory control tasks. Results: The results showed that working memory was significantly related to source monitoring regardless of the condition of source recall (continuous vs non-continuous). On the other hand, inhibitory control was significantly associated with source monitoring only in the non-continuous source recall group. Conclusion: Based on these results, the author discussed the need to consider the conditions of source recall during investigative interviews with children in order to induce accurate source monitoring, as part of our effort to interpret the inconsistency of results in the literature and to draw potential applications.

• Korean Journal of Cognitive Science
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• v.33 no.1
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• pp.23-50
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• 2022

Source memory is a cognitive process that combines the representation of the origin of the episodic experience with an item. By studying this daily process, researchers have made fundamental discoveries that make up the foundation of brain and behavior research, such as executive function and binding. In this paper, we review and conduct a bibliometric analysis on source memory papers published from 1989 to 2020. This review is based on keyword co-occurrence networks and author citation networks, providing an in-depth overview of the development of source memory research and future directions. This bibliometric analysis discovers a change in the research trends: while research prior to 2010 focused on individuality of source memory as a cognitive function, more recent papers focus more on the implication of source memory as it pertains to connectivity between disparate brain regions and to social neuroscience. Keyword network analysis shows that aging and executive function are continued topics of interest, although frameworks in which they are viewed have shifted to include developmental psychology and meta memory. The use of theories and models provided by source memory research seem essential for the future development of cognitive enhancement tools within and outside of the field of Psychology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.26-31
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• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.413-416
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• 1998

This paper presents a dAC calibration technique for high resolution and monolithic operation. The calibration technique consists of basic source, current memory cell (C.M) and current substrator. Current memory supplies the error current to basic source. Current substrator extracts the error current from the main source. It is simple and needs no special calibration period. The proposed current cell has high calibration performance and guarantees 100MHz operation.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.675-688
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• 2007

Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.70-79
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• 1996

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.