• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• 한국표면공학회지
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• 제50권3호
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• pp.155-163
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• 2017

In this study, the effects of the concentration of metal ions and the applied current density in the Sn-Ag plating solutions were examined in regards to the resulting composition and morphology of the solder bumps' surface. Furthermore the effect of any impurities present in the methanesulfonic acid used as a base acid in the Sn-Ag solder plating solution on the stability of plating solution as well as the characteristics of the Sn-Ag alloys films was also explored. As expected, the uniform bump was obtained by means of removing impurities in the plating solution. Consequently the resultant solder bump was obtained in an optimal current density of the range of $1A/dm^2$ to $15A/dm^2$, which has acceptable bump shape and surface roughness with 12inch wafer trial results.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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• pp.456-462
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• 2002

In the present work, a low cost and fine pitch bumping process by electroless Ni/immersion Au UBM (under bump metallurgy) and stencil printing for the solder bump on the Al pad is discussed. The Chip used this experimental had an array of pad 14x14 and zincate catalyst treatment is applied as the pretreatment of Al bond pad, it was shown that the second zincating process produced a dense continuous zincating layer compared to first zincating. Ni UBM was analyzed using Scanning electron microscopy, Energy dispersive x-ray, Atomic force microscopy, and X-ray diffractometer. The electroless Ni-P had amorphous structures in as-plated condition. and crystallized at 321 C to Ni and Ni$_3$P. Solder bumps are formed on without bridge or missing bump by stencil print solder bump process.

• 마이크로전자및패키징학회지
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• 제8권1호
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• pp.45-51
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• 2001

UBM층과의 젖음 특성 및 표면 산화정도가 미세 피치를 갖는 저 융점 솔더 범프의 볼 형성에 미치는 영향을 연구하였다. Au/Cu/Cr 과 Au/Ni/Ti UBM 위에 공정 조성에 가까운 In-Ag와 공정 조성의 Bi-Sn 솔더를 솔더 층의 증착 순서를 달리하여 증발 증착한 후 lift-off 공정과 열처리 공정을 사용하여 솔더 범프를 형성하였다. In-Ag솔더의 경우 In이 UBM 층과 접한 범프가, 또한 Bi-Sn 솔더의 경우 Sn을 먼저 UBM층위에 먼저 증착시켜 리플로 한 범프가 솔더 볼 형성 경향이 다른 범프에 비해 높았다. 구형의 솔더 범프 형성 정도는 UBM 층과의 젖음 특성에 따라 크게 달라졌다.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.82-82
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• 1995

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.245-247
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• 2007

Sn-base solder bump is mainly used in micro-joining for flip chip package. The quantity of intermetallic compounds that was formed between Cu pad and solder interface importantly affects reliability. In this research, micro-bump was fabricated by two binary electroplating and the intermetallic compounds(IMCs) was estimated quantitatively. When the micro Sn-Ag solder bump was made by electroplating, SiC powder was added in the plating solution for protecting of intermetallic growth. Then, the intermetallic compounds growth was decrease with increase of amount of SiC power. However, if the mount of SiC particle exceeds 4 g/L, the effect of the growth restraint decrease rapidly.

• 한국정밀공학회지
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• 제31권10호
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.1005-1008
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• 2003

We report a new FCOG (flip chip on glass) technique using solder bumps for display packaging applications. The In and Sn solder bumps of 40 ${\mu}m$ pitches were formed on Si and glass substrate. The In and Sn bumps were bonded at 125 at the pressure of 3 mN/bump. The metallurgical bonding was confirmed using cross-sectional SEM. The contact resistance of the solder joint was 65 $m{\Omega}$ which was much lower than that of the joint made using the conventional ACF bonding technique. We demonstrate that the new COG technique using solder bump to bump direct bonding can be applied to advanced LCDs that lead to require higher quality, better resolution, and lower power consumption.

• 마이크로전자및패키징학회지
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• 제5권1호
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• pp.7-18
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• 1998

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as 1$\mu$m Al/0.2$\mu$m Pd/1$\mu$m Cu, laid under eutectic Pb/Sn solder were investigated with regard to their interfacial reactions and adhesion proper-ties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMCs) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1$\mu$m Al/0.2$\mu$m Ti/5$\mu$m Cu and 1$\mu$m Al/0.2$\mu$m ni/1$\mu$m Cu even after 4 solder reflows or 7 day aging at 15$0^{\circ}C$. In contrast 1$\mu$m Al/0.2$\mu$m Ti/1$\mu$m Cu and 1$\mu$mAl/0.2$\mu$m Pd/1$\mu$m 쳐 show poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. In this case thin 1$\mu$m Cu and 0.2$\mu$m Pd diffusion barrier layer were completely consumed by Cu-Sn and pd-Sn reaction.