• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.469-470
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• 2012

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.285-286
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• 2015

반도체 패키지 솔더범프용 주석계 도금액에 적용 가능한, 친환경 산화방지제 몇 종에 대하여 연구하였다. 주석계 전기도금액에 포함된 산화방지제는 주석의 산화방지 외에도, 전류효율, 도금액의 안정성, 그리고 형성된 솔더범프의 특성 등에 영향이 있음을 확인 하였다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.2
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• pp.1-9
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• 2002

The intermetallic formation between Sn-Ag-(Cu) solders and metal pads in a real BGA package was characterized using SEM, EDS, and XRD. The intermetallic phase formed in the interface between Sn-Ag-Cu and Au/Ni/Cu pad is likely to be ternary compound of $(Cu,Ni)_6Sn_5$ from EDS analysis High concentration of Cu was observed in the solder/Ni interface. XRD analysis confirmed that $\eta -Cu_6 Sn_5$ type was intermetallic phase formed in the interface between Cu containing solders and Ni substrates and $Ni_3$Sn_4$ intermetallic was formed in the Sn-Ag solder/Ni interface. The thickness of intermetallic phase increased with the reflow times and Cu concentration in solder.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.1-6
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• 2004

The requirements for harsh environment electronic controllers in automotive applications have been steadily becoming more and more stringent. Electronic substrate technologists have been responding to this challenge effectively in an effort to meet the performance, reliability and cost requirements. An effect of the plasma cleaning at the ECM(Engine Control Module) alumina substrate and the intermetallic compound layer between Sn-37wt%Pb solder and pad joints after reflow soldering has been studied. Organic residual carbon layer was removed by the substrate plasma cleaning. So the interfacial adhesive strength was enhanced. As a result of AFM measurement, conductor pad roughness were increased from 304 nm to 330 nm. $Cu_6/Sn_5$ formed during initial reflow process at the interface between TiWN/Cu pad and solder grew by the succeeding reflow process, so the grains became coarse. A cellular-shaped $Ag_3Sn$ was observed at the interface between Ag-Pd conductor pad and solder. The diameters of the $Ag_3Sn$ grains ranged from about 0.1∼0.6 $\mu\textrm{m}$. And a needle-shaped was also observed at the inside of the solder.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.82-82
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• 2010

표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.25-31
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• 2010

In this study, we investigated the morphology and thermal stability of interfacial phases in joint between lead free solder(Sn-3.0Ag-0.5Cu) and electroless Ni-W-P under bump metallizations(UBM) with different tungsten contents as a function of thermal aging. Content of phosphorus of each deposits was fixed at 8 wt.%, and content of tungsten was variated each 0, 3, 6 and 9 wt.%. Specimens were prepared by reflowing at $255^{\circ}C$, aging range was $200^{\circ}C$ and up to 2 weeks. After reflow process, in the electroless Ni(W)-P/solder joint, the interfacial intermetallic compound(IMC) was showed both $(Cu,Ni)_6Sn_5$ and $(Ni,Cu)_3Sn_4$. UBM and generated IMC at the interface of lead free solder was proportionally increased with aging time. The thickness of IMC was increased because the generation rate of $Ni(W)_3P$ decreased with increasing contents of W.