• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Electrical & Electronic Materials
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• v.6 no.6
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• pp.505-513
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• 1993

본 논문은 전자 부품의 Soldring기에 사용되는 접합제를 Flux를 포함한 Solder paste 대신에 도금막을 이용하기 위한 Sn 도금막 형성 프로세스를 검토한 것이다. 반도체 Device를 Packaging한 외부단자(lead frame)과 HIC상의 후막전극(Ag/Pd)과의 접합 및 PCB상의 Cu land와의 접합시에는 스크린 프린트에 의한 Solder Paste가 일반적으로 사용되고 있다. 본 논문은 Fluxless Soldering의 한수단으로 도금막을 lead상에 형성시켜 접합 재료로서의 형성 프로세스 및 도금막의 특성과 도금형성 Paramete와의 관련성을 실험적으로 검토한 것으로 전류밀도 200 A/m$^{2}$의 조건으로 형성한 Sn 도금막이 접합용으로 최적조건임을 밝혔다.

• Journal of Welding and Joining
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• v.29 no.5
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• pp.95-98
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• 2011

Recently, there is a growing tendency that fine-pitch electronic devices are increased due to higher density and very large scale integration. Finer pitch printed circuit board(PCB) is to be decrease insulation resistance between circuit patterns and electrical components, which will induce to electrical short in electronic circuit by electrochemical migration when it exposes to long term in high temperature and high humidity. In this research, the effect of soldering flux acting as an electrical carrier between conductors on electrochemical migration was investigated. The PCB pad was coated with OSP finish. Sn3.0Ag0.5Cu solder paste was printed on the PCB circuit and then the coupon was treated by reflow process. Thereby, specimen for ion migration test was fabricated. Electrochemical migration test was conducted under the condition of DC 48 V, $85^{\circ}C$, and 85 % relative humidity. Their life time could be increased about 22% by means of removal of flux. The fundamentals and mechanism of electrochemical migration was discussed depending on the existence of flux residues after reflow process.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.64-72
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• 2023

In this study, after transferring graphene on a Cu substrate and printing a Sn-3.0Ag-0.5Cu Pb-free solder paste on the Cu substrate, effects of the transferred graphene on formations and growths of intermetallic compound (IMC) at the interface between the Cu substrate and the solder were reported during processes of reflow soldering and isothermal aging for 1000 h with various temperatures (125, 150, and 175 ℃). Thicknesses of Cu₆Sn₅ and Cu₃Sn IMCs at the interfaces with graphene were decreased during the reflow soldering and isothermal aging processes compared to those without graphene. The transferred graphene layers also showed that the growth rate constant and square of growth rate constant which related to the growth mechanisms of Cu₆Sn₅ and Cu₃Sn IMCs with t he t emperature a nd t ime of t he i sothermal aging c ould dramatically decreased.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.123-128
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• 2018

Effect of activators in flux on the printability and wettability of a solder paste was evaluated in this study. The activators in this study were dicarboxylic acids, which were oxalic acid (n = 0), malonic acid (n = 1), succinic acid (n = 2), glutaric acid (n = 3), adipic acid (n = 4), and pimelic acid (n = 5). When the solder pastes were observed with a SMT scope, solder with glutaric acid showed clean and shiny surface when it was melted. Slump ratio of the solder pastes was low when the carbon numbers of the dicarboxylic acid were 1-3. Spreadability was high when the carbon number was over 2. Zero cross time of wetting balance test was under 1 sec when the carbon number was over 3. When activator was oxalic acid or malonic acid, zero cross time was over 1 sec and maximum wetting force was low. Fluxes with the oxalic acid and malonic acid showed decomposition at the temperature close to melting point. Among the dicarboxylic acids, glutaric acid provided excellent slump, spreadability, and wettability.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.76-76
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• 2009

눈부신 전자산업의 발달로 대부분의 전자제품이 다기능/경박단소화 되고 있어, 고밀도 실장 기술인 양면 표면실장과 고집적 패키징 기술인 패키지 적층 공정의 적용이 점차 확대되고 있다. 따라서 양면 표면실장 및 패키지 적층 공정에 사용되는 저온 접합용 무연 솔더 즉, $183^{\circ}C$(Sn-37Pb 공정 솔더 융점) 이하의 융점을 가지는 저온 무연 솔더에 대한 관심이 높아지고 있다. 한편, 미세피치 적용 분야에 있어 ACF/P를 이용한 COG 접속 분야 외에도 최근 저온 접합용 무연 솔더를 이용한 접속 분야가 각광을 받고 있다. 따라서, 접속피치 미세화에 대응하기 위해 스크린 인쇄성을 향상시킬 수 있는 저온 무연 솔더 paste 제조 및 공정 기술의 개발이 필요한 실정이다. 현재 대표적인 저온 무연 솔더 조성은 Sn-Bi계($138^{\circ}C$ 융점)와 Sn-In계($120^{\circ}C$ 융점)이다. 하지만, 이들 조성의 신뢰성 등에 있어 개선의 여지가 있으므로 이를 해결하기 위한 무연솔더 조성의 개발이 필요하다. 이와 같은 관점에서, 본 연구는 $137^{\circ}C$의 융점을 갖는 Sn-57.6Ag-0.4Ag 저온 무연 솔더 paste를 $217^{\circ}C$의 융점을 갖는 Sn-3.0Ag-0.5Cu 솔더 paste와 비교하여 인쇄성, reflow 특성, void inspection, 미세조직 관찰 및 underfill 적용 등의 실험을 실시하였다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.71-77
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• 2011

Main parameters of the screen printing were determined and the printing parameters were optimized for 0402, 0603, and 1005 chips in this study. The solder pastes used in this study were Sn-3.0Ag-0.5Cu and Sn-0.7Cu. The process parameters were stencil thickness, squeegee angle, printing speed, stencil separating speed and gap between stencil and PCB. The printing pressure was fixed at 2 $kgf/cm^2$. From ANOVA results, the stencil thickness and the squeegee angle were determined to be main parameters for the printing efficiency. The printing efficiency was optimized with varying two main parameters, the stencil thickness and the squeegee angle. The printing efficiency increased as the squeegee angle was lowered under 45o for all chips. For the 0402 and the 0603 chips, the printing efficiency increased as the stencil thickness decreased. On the other hand, for the 1005 chip, the printing efficiency increased as the stencil thickness increased.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.65-70
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• 2021

In this study, interfacial properties and mechanical properties of joints were reported after Cu pads finished with organic solderability preservative (OSP) on flame retardant-4 (FR-4) printed circuit board (PCB) and electronic components were joined with a Sn-57Bi-1Ag solder paste by using a laser bonding process. The laser bonding process was performed under various bonding conditions with changing a laser power and a bonding time and effects of bonding conditions on interfacial and mechanical properties of joints were analyzed. In order to apply for industry, properties of bonding joints using a reflow bonding process which are widely used were compared. When the laser bonding process were performed, we observed that Cu₆Sn₅ intermetallic compounds (IMCs) were fully formed at the interface although the bonding times were very short about 2 and 3 s. Furthermore, void formations of the joints by using the laser bonding process were suppressed at the joints with comparing to the reflow bonding process and shear strengths of bonding joints were higher than that by using the reflow bonding process. Therefore, in spite of a very short bonding time, it is expected that joints will be stably formed and have a high mechanical strength by using the laser bonding process.