• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.23 no.7
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• pp.513-519
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• 2011

The object of this study is to investigate the performance characteristics of refrigerators using a single-circuit multi cycle and a bypass two-circuit multi cycle. Each refrigeration cycle was tested by varying secondary fluid mass flow rate and temperature. Based on the experimental data, the optimum refrigerant charge was 48 g and the COP at the optimum secondary fluid mass flow rate was 1.53 for the single-circuit multi cycle. For freezer(F)-only mode, both the single-circuit multi cycle and the bypass two-circuit multi cycle were operated at overcharge conditions, resulting in an increase of the secondary fluid mass flow rate. The maximum COPs of the single-circuit multi cycle and the bypass two-circuit multi cycle were 1.22 and 1.35, respectively. The COP increased by 10.7% with the application of the bypass two-circuit multi cycle.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• 한국지구물리탐사학회:학술대회논문집
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• 2003.11a
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• pp.518-521
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• 2003

LCA (Life Cycle Assessment), that unifies the scale of various environmental impacts, and simulated annealing are applied to optimizing electrolysis of wastewater from PCB (Printed Circuit Board) production. The changes of environmental impact can be quantified with LCA and the total changes of environmental impacts can be expressed as a function of power consumed, Cu recycled, $Cl_2$, NOx and SOx discharged through restriction of feasible reactions. In a single-variate condition, the environmental optimum can be easily obtained through plotting and comparing each environmental impact value. In 8V potentiostatic electrolysis, the lowest environmental impact can be achieved after 90min. To optimize a multi-variate conditional system, simulated annealing can be applied and this can give the quick and near optimum in complex systems, where many input and output materials are involved, through experimentally measured values without a theoretical modeling.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.125-128
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• 2006

This paper presents a novel type soft switching PWM power frequency AC-AC converter using bidirectional active switches or single phase utility frequency AC-high frequency AC matrix converter. This converter can directly convert utility frequency AC (UFAC, 50Hz/60Hz) power to high frequency AC (HFAC) power ranging more than 20kHz up to 100kHz. A novel soft switching PWM prototype of high frequency multi-resonant PWM controlled UFAC-HFAC matrix converter using antiparallel one-chip reverse blocking IGBTs manufactured by IXYS corp. is based on the soft switching resonance with asymmetrical duty cycle PWM strategy. This single phase UFAC-HFAC matrix converter has some remarkable features as electrolytic capacitor DC busline linkless topology, unity power factor correction and sine-wave line current shaping, simple configuration with minimum circuit components, high efficiency and downsizing. This series load resonant UFAC-HFAC matrix converter, incorporating bidirectional active power switches is developed and implemented for high efficiency consumer induction heated food cooking appliances in home uses and business-uses. Its operating performances as soft switching operating ranges and high frequency effective power regulation characteristics are illustrated and discussed on the basis of simulation and experimental results.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.