• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.188-198
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• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1491-1493
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• 2000

Continuing improvement of microprocessor performance involves in the device size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. So, MSSQ which has the permittivity between 2.5-3.2 is used to prevent from these problems. For pattering MSSQ(Methylsilsequioxane), we use RIE(Reactive Ion Etching) and MERIE(Magnetically enhanced Reactive Ion Etching) which could provide good anisotropic etching. In this study, we optimized the flow rate of $CF_{4}/O_2$ gas, RF power to obtain the best etching rate and roughness and also analyzed the etching result using $\alpha$-step profilemeter, SEM, infrared spectrum and AFM.

• Journal of the Korean Magnetics Society
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• v.18 no.1
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• pp.28-31
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• 2008

We studied the effect of easy magnetization axis orientation with respect to the strip direction by measuring the magnetoresistance(MR), the magneto-optic Kerr effect(MOKE), and real-time domain evolution. The five strips were patterned on a single chip with the easy axis orientation of each strip relative to the longitudinal direction by around $0^{\circ}$, $18^{\circ}$, $36^{\circ}$, $54^{\circ}$ and $72^{\circ}$, respectively. The overall shape of field dependent MR was mostly governed by the anisotropy magnetoresistnace. The relative change of the longitudinal MR was significantly increased with increasing angle between the easy axis and strip direction, whereas, the transverse MR variation rate was decreased with increasing angle. Several MR steps were observed during the magnetization reversal, and the simultaneous measurement of the MOKE and the domain images identified that the MR steps were associated with evolution of the oppositely directed magnetic domain.

• International Journal of Railway
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• v.3 no.2
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• pp.39-45
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• 2010

The RF-CBTC (Radio Frequency-Communication Based Train Control) System is a communication system in railroad systems. The communication method of RF-CBTC system is the wireless between the wayside device and on-board device. The wayside device collects its location and speed from each train and transmits the distance from the forwarding train to the speed-limit position to it. The on-board device controlling device controls the speed optimum for the train. In the case of the RF-CBTC system used in Korea, transmission frequency is 2.4 [GHz]. It is the range of ISM(Industrial Scientific and Medical equipment) band and transmission of voice and data is performed by CDMA (Code Division Multiple Access) method. So noises are made in the AWGN (Additive White Gaussian Noise) and fading environment. Currently, the SNR (Signal to Noise Ratio) is about 20 [dB], so due to bit errors made by noises, transmission of reliable information to the train is not easy. Also, in the case that two tracks are put to a single direction, it is needed that two trains transmit reliable voice and data to a wayside device. But, by noises, it is not easy that just a train transmits reliable information. In this paper, we estimated the BER (Bit Error Rate) related to the SNR of voice and data transmission in the environment such as AWGN and fading from the RF-CBTC system using the CDMA method. Also, we supposed the SNR which is required to meet the BER standard for voice and data transmission. By increasing the processing gain that is a ratio of chip transmission to voice and data transmission, we made possible voice and data transmission from maximally two trains to a wayside device, and demonstrated it by using Matlab program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.1068-1076
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.