• 제목/요약/키워드: Single-Point Design

검색결과 518건 처리시간 0.023초

Attitude control in spacecraft orbit-raising using a reduced quaternion model

  • Yang, Yaguang
    • Advances in aircraft and spacecraft science
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    • 제1권4호
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    • pp.427-441
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    • 2014
  • Orbit-raising is an important step to place spacecraft from parking orbits into working orbits. Attitude control system design is crucial in the success of orbit-raising. Several text books have discussed this design and focused mainly on the traditional methods based on single-input single-output (SISO) transfer function models. These models are not good representations for many orbit-raising control systems which have multiple thrusters and each thruster has impact on the attitude defined by all outputs. Only one published article is known to use a more suitable multi-input multi-output (MIMO) Euler angle model in spacecraft orbit-raising attitude control system design. In this paper, a quaternion based MIMO model for the orbit-raising attitude control system design is proposed. The advantages of using quaternion based model for orbit-raising control system designs are (a) there is no need for mathematical transformations because the attitude measurements are normally given by quaternion, (b) quaternion based model does not depend on rotational sequences, which reduces the chance of human errors, and (c) the singular point of reduced quaternion model is the farthest from the operational point where linearization is performed. We will show that performance of quaternion model based design will be as good as the performance of Euler angle model based design for orbit-raising problem.

ARM 프로세서용 부동 소수점 보조 프로세서 개발 (Development of a Floating Point Co-Processor for ARM Processor)

  • 김태민;신명철;박인철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.232-235
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    • 1999
  • In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

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압축기 설계조건이 가스터빈 엔진의 탈설계점 성능에 미치는 영향 (The Effects of Compressor Design Conditions on the Off-Design Performance of a Gas Turbine Engine)

  • 강동진;정평석;안상규
    • 대한기계학회논문집
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    • 제18권9호
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    • pp.2413-2422
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    • 1994
  • The effects of compressor design conditions on the off-design performance of a single-shaft gas turbine engine have been studied. Three different geometric design conditions are considered and three different values for the specific mass flow rate at the inlet to the compressor are assumed. For each of nine compressor design, the off-design performance of the gas turbine engine is predicted using the method previously proposed by present authors. Results show that the predicted off-design performances are quite different from each other even though they have the same performance at design point: it means that compressor design conditions should be determined in consideration of the off-design performance of the engine. The specific mass flow rate at the inlet to the compressor is also shown that it might be optimized with respect to the net power of the engine.

단상 BLDC 전동기의 코깅토크 저감을 위한 고정자 형상 최적설계 (Optimal Design of Stator Shape for Cogging Torque Reduction of Single-phase BLDC Motor)

  • 박용운;소지영;정동화;유용민;조주희;안강순;김대경
    • 전기학회논문지
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    • 제62권11호
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    • pp.1528-1534
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    • 2013
  • This paper proposes the optimal design of stator shape for cogging torque reduction of single-phase brushless DC (BLDC) motor with asymmetric notch. This method applied size and position of asymmetric notches to tapered teeth of stator for single-phase BLDC motor. Which affects the variation of the residual flux density of the permanent magnet. The process of optimal design included the extraction of the sampling point by using Latin Hypercube Sampling(LHS), and involved the creation of an approximation model by using kriging method. Also, the optimum point of the design variables were discovered by using the Genetic Algorithm(GA). Finite element analysis was used to calculate the characteristics analysis and cogging torque. As a result of finite element analysis, cogging torque were reduced approximately 39.2% lower than initial model. Also experimental result were approximately 38.5% lower than initial model. The period and magnitude of the cogging torque were similar to the results of FEA.

Single-Balanced Low IF Resistive FET Mixer for the DBF Receiver

  • Ko Jee-Won;Min Kyeong-Sik
    • Journal of electromagnetic engineering and science
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    • 제4권4호
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    • pp.143-149
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    • 2004
  • This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

IEEE 754-1985 단정도 부동 소수점 연산용 나눗셈기 설계 (Design of a Floating-Point Divider for IEEE 754-1985 Single-Precision Operations)

  • 박안수;정태상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.165-168
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    • 2001
  • This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

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A design of a floating point unit with 3 stages for a 3D graphics shader engine

  • Lee, Kwang-Yeob
    • 전기전자학회논문지
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    • 제11권4호
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    • pp.358-363
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    • 2007
  • This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

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임무컴퓨터를 위한 고가용 시스템의 설계 및 구현 (Design and Implementation of High-availability System)

  • 정재엽;이철훈
    • 한국콘텐츠학회:학술대회논문집
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    • 한국콘텐츠학회 2008년도 춘계 종합학술대회 논문집
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    • pp.529-533
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    • 2008
  • 임무컴퓨터는 항공전자시스템에서 전체 시스템을 관리하고, 특정 임무를 처리하는 중요한 역할을 수행한다. 일반적으로 단일 시스템에서 SPOF(Single Point Of Failure) 요소의 고장은 전체 시스템의 고장으로 이어질 수 있으며, 이는 서비스의 중단으로 인한 임무의 실패뿐만 아니라 조종사의 생명까지도 위협할 수 있다. 이에 본 논문에서는 SPOF 요소를 제거하기 위해 단일 시스템을 이중화하여 고장발생에 유연하게 대처하도록 설계하였다. 또한 이를 효율적으로 운영하기 위한 방안으로 리눅스 기반의 Heartbeat, Fake, DRBD(Distributed Replicated Block Device), Bonding 등의 기법을 이용하여 시스템을 관리한다.

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Equivalent static wind load estimation in wind-resistant design of single-layer reticulated shells

  • Li, Yuan-Qi;Tamura, Yukio
    • Wind and Structures
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    • 제8권6호
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    • pp.443-454
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    • 2005
  • Wind loading is very important, even dominant in some cases, to large-span single-layer reticulated shells. At present, usually equivalent static methods based on quasi-steady assumption, as the same as the wind-resistant design of low-rise buildings, are used in the structural design. However, it is not easy to estimate a suitable equivalent static wind load so that the effects of fluctuating component of wind on the structural behaviors, especially on structural stability, can be well considered. In this paper, the effects of fluctuating component of wind load on the stability of a single-layer reticulated spherical shell model are investigated based on wind pressure distribution measured simultaneously in the wind tunnel. Several methods used to estimate the equivalent static wind load distribution for equivalent static wind-resistant design are reviewed. A new simple method from the stability point of view is presented to estimate the most unfavorable wind load distribution considering the effects of fluctuating component on the stability of shells. Finally, with comparisive analyses using different methods, the efficiency of the presented method for wind-resistant analysis of single-layer reticulated shells is established.

린 프로세스 기반 아웃리거 시스템의 Set-based Design 적용 방안에 관한 연구 (A Study on the Application Methodology of Set-based Design Approach of Outrigger System based on Lean Process)

  • 이승일;조영상
    • 한국건설관리학회논문집
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    • 제12권4호
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    • pp.50-58
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    • 2011
  • 린은 고객이 정하는 가치를 정의하고 가치의 흐름에 방해되는 불필요하고 낭비되는 요소를 없애는 과정을 기본으로 하는 경영철학이다. 생산관리에서 출발한 린이라는 경영철학은 건설 산업에서“린 건설”이라는 이름으로 건설단계에서 시작되었으며 이제는 생산성 향상을 효과적으로 이룰 수 있는 설계단계로의 확장이 필요한 시점이다. 현재 국내의 구조설계업무방식은 순차적 공학 개념의 Point-based Design 방식으로 설계자의 경험과 판단에 의존하여 초기 설계안을 결정하고 이후 상세설계를 진행하는 과정으로 설계업무가 진행되었다. 이에 반해 동시공학 개념의 Set-based Design 방식은 전체 프로젝트 관점에서 낭비요소를 없애고 프로젝트 생산성 향상을 위해 다양한 설계안을 제한된 범위 내에서 바로 선택하지 않고 더 확실한 정보가 나올 때까지 설계안의 선택을 유보하여 합리적이고 경제적인 설계안을 결정하는 린 기반의 설계 프로세스이다. 본 연구에서는 전통적인 구조설계방식에 대해 SBD방식을 도입하고, SBD프로세스의 의사결정기법으로 계층화분석법(AHP)을 적용하여, 후행업무단계들에 대한 사전 고려로 프로젝트 전체 관점에서의 낭비를 최소화하고 생산성을 향상할 수 있는 설계 방법론을 제안하고 하고자 한다. 이를 위해 PBD와 SBD방식에 대한 분석 및 의사결정방안을 모색하였고, 제안된 SBD프로세스의 사례연구를 통해 실무에서의 활용방안을 제시하였다.