• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.192-193
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• 2007

An evaporated Ti/Pd/Ag contact system is most widely used to make high-efficiency silicon solar cells, however, the system is not cost effective due to expensive materials and vacuum techniques. Commercial solar cells with screen-printed contacts formed by using Ag paste suffer from a low fill factor and a high shading loss because of high contact resistance and low aspect ratio. Low-cost Ni and Cu metal contacts have been formed by using electro less plating and electroplating techniques to replace the Ti/Pd/Ag and screen-printed Ag contacts. Ni/Cu alloy is plated on a silicon substrate by electro-deposition of the alloy from an acetate electrolyte solution, and nickel-silicide formation at the interface between the silicon and the nickel enhances stability and reduces the contact resistance. It was, therefore, found that nickel-silicide was suitable for high-efficiency solar cell applications. Cu was electroplated on the Ni layer by using a light induced plating method. The Cu electroplating solution was made up of a commercially available acid sulfate bath and additives to reduce the stress of the copper layer. In this paper, we investigated low-cost Ni/Cu contact formation by electro less and electroplating for crystalline silicon solar cells.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.619-622
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• 2005

본 논문에서는 서로 다른 Si 두께 ($T_{Si}$ = 27, 50 nm) 를 갖는 SOI (Silicon On Insulator) 기판 위에 다양한 두께의 Ni/Co를 순차적으로 증착한 후 Bulk-Si과의 비교를 통해 Silicide의 형성 특성에 대하여 분석하였다. 우선 급속 열처리 (RTP, Rapid Thermal Processing) 를 통하여 Silicide를 형성한 후 측정결과 Si두께에 따라 Silicide의 특성이 달라짐을 확인하였다. 두꺼운 두께의 Si-film을 갖는 SOI 기판을 사용한 경우 증착된 금속의 두께에 따라 Bulk-Si와 비슷한 면저항 특성을 보였으나, 얇은 두께의 Si-film을 갖는 SOI기판을 사용한 경우에는 제한된 Si의 공급으로 인한 Silicide의 비저항 증가로 인하여 증착된 금속의 두께에 따라 면저항이 감소하다가 다시 증가하는 'V' 자형 곡선을 나타내었다.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.528-537
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• 2008

60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm $SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-$SiO_2$/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from $400^{\circ}C$ which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from $300^{\circ}C$. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at $300^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.167-170
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• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.109-109
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• 2000

Recently, carbon nanotube has been investigating for field emission display ( (FED) applications due to its high electron emission at relatively low electric field. However, the growing of carbon nanotube generally requires relatively high temperature processing such as arc-discharge (5,000 ~ $20,000^{\circ}C$) and laser evaporation (4,000 ~ $5,000^{\circ}C$) methods. In this presentation, low temperature growing of carbon nanotube by plasma enhanced chemical vapor deposition (PECVD) using nickel catalyst which is compatible to conventional FED processing temperature will be described. Carbon n notubes with average length of 100 run and diameter of 2 ~ $3\mu$ill were successfully grown on silicon substrate with native oxide layer at $550^{\circ}C$using nickel catalyst. The morphology and microstructure of carbon nanotube was highly depended on the processing temperature and nickel layer thickness. No significant carbon nanotube growing was observed with samples deposited on silicon substrates without native oxide layer. This is believed due to the formation of nickel-silicide and this deteriorated the catalytic role of nickel. The formation of nickel-silicide was confirmed by x-ray analysis. The role of native oxide layer and processing parameter dependence on microstructure of low temperature grown carbon nanotube, characterized by SEM, TEM XRD and R없nan spectroscopy, will be presented.

• Korean Journal of Materials Research
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• v.1 no.2
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• pp.99-104
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• 1991

Trantalum thin films have been prepared by DC sputtering onto As, P, and $BF_2$-implanted ($5{\times}10^15cm^-2$) poly-silicon. The heat treatments by rapid thermal annealing(RTA) have been applied to these samples for the formation of silicides. We have studied the application possibility of Ta-silicide as gate electrode and bit line. The silicide formation and the dopant diffusion after the heat treatment were investigated by various methods, such as four-point probe, X-ray, SEM cross sectional views, ${\alpha}$-step, and SIMS, The tantalum disilicide($TaSi_2$) are formed in the temperature above $800^{\circ}C$, and grown in colummar structure. $TaSi_2$ has a good surface roughness, having range from $80{\AA}\;to\;120{\AA}$, and implanted dopants are incoporated into the $TaSi_2$ layer during the RTA temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.405-408
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• 1998

In this paper, We analyzed the current-voltage characteristics with n-type silicon substrates concentration and temperature variations (Room temperature, 5$0^{\circ}C$, 75$^{\circ}C$) in platinum silicide and silicon junction. Measurement electrical parameters are forward turn-on voltage, reverse breakdown voltage, barrier height, saturation current, ideality factor, dynamic resistance acceding to junction concentration of substrates and temperature variations. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height and dynamic resistance were decreased but saturation current and ideality factor were increased by substrates concentration variations. Reverse breakdown voltage and dynamic resistance were increased by temperature variations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.270-272
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• 2005

The behavior of surface oxidation on cobalt silicide layer was investigated under rapid thermal oxidation (RTO) conditions. The cobalt silicide layer was prepared on p-type silicon substrates. We used Ti thin film as a capping layer in order to measure the degree of oxidation of the layer. Oxide grew faster on the cobalt silicide prepared with the Ti capping layer to reach ca $500{\AA}$ at $700^{\circ}C$ in thickness. The oxide film kept growing under $550^{\circ}C\~700^{\circ}C$ of the RTO condition, resulting in a saturated state above $500{\AA}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.575-579
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• 2010

The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.