• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1072-1074
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• 1995

Zinc-Borosilicate is used as a side insulastor wall to make high breakdown voltage with one Field Limiting Ring in a p-n junction. It is known that surface charge can be yield at the interface of Zinc-Borosilicate Glass/Silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage improved more than 660V without using more FLR.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.692-696
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• 2005

In an attempt to fabricate all inclusive display systems we are presenting a study on several elements that would be used as building blocks for all-on-board integrated applications on stainless steel foils. These systems would include in the same substrate all or many of the components needed to drive a flat panel OLED display. We are reporting results on both digital and analog circuits on stainless steel foils. Shift registers running at speeds greater than 1.0MHz are shown as well as oscillators operating at over 40MHz. Pixel circuits for driving organic light emitting diodes are presented. The device technology of choice is that based on poly-silicon TFT technology as it has the potential of producing circuits with good performance and considerable cost savings over the established processes on quartz or glass substrates (amorphous Silicon a-Si:H or silicon on Insulator SOI).

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.11
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• pp.483-489
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• 2005

This study performs a simulation for an accumulation mechanism of contaminants, which were produced in an industrial belt of inland, on the surface of insulators. From the simulation, silicon insulators presented higher accumulation than that of EPDM(Ethylene Propylene Diene Terpolymer : EPDM) insulators on the same distance in the case of the Virgin polymer insulator, and this result presented the same result in the insulator applied in actual fields. In the case of the accumulation test for the Virgin insulator and insulators used in actual fields, it is evident that the Virgin insulator presented more accumulation than that of the insulator used in actual fields. The results can be caused by the generation of LMW (Low Molecular Weight) on the external material of polymer insulators, and the level of the accumulation can be changed according to the degree of the continuous generation of LMW. In order to simulate a certain pollution of an industrial belt, which is located along the coastline, leakage currents were measured by applying the contaminant compulsively that was produced with salts and Kaolin according to the ratio of its weight on the surface of insulators. The more increase in the content of Kaolin pollution, the level of leakage currents on the surface of polymer insulator more increased. In addition, the approaching time to the maximum value of leakage currents presented a nearly constant level regardless of the content of Kaolin. The level of leakage currents significantly decreased according to the passage of time, and the level of leakage currents on the surface maintained a constant level at a specific time regardless of the content of Kaolin.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2000.05a
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• pp.105-109
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• 2000

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor the size of the pressure sensor diaphragm have become smaller year by year and a microaccelerometer with a size less than 200-300${\mu}m$ has been realized. In this paper we study some of the micromachining processes of SOI(silicon on insulator)for the microaccelerometer and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in structural engineering discipline for design of SOI wafers. Successful thermal behaviors analysis and design of the SOI wafers based on the tunneling current concept using SOI wafer depend on the knowledge abut normal mechanical properties of the SCS(single crystal silicon)layer and their control through manufacturing process

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.7
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• pp.424-432
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• 2000

The plasma surface treatment, using hydrogen gas, of the silicon wafer was investigated as a pretreatment for the application to silicon-on-insulator (SOI) wafers using the silicon direct bonding technique. The chemical reactions of hydrogen plasma with surfaces were used for both the surface activation and the removal of surface contaminants. As a result of exposure of silicon wafer to the plasma, an active oxide layer was formed on the surface, which was rendered hydrophilic. The surface roughness and morphology were estimated as functions of plasma exposing time as well as of power. The surface became smoother with decreased incident hydrogen ion flux by reducing plasma exposing time and power. This process was very effective to reduce the carbon contaminants on the silicon surface, which was responsible for a high initial surface energy. The initial surface energy measured by the crack propagation method was 506 mJ/m2, which was up to about three times higher than that of a conventional RCA cleaning method.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.106-107
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• 2000

현대 사회의 정보서비스 수요 증가는 1990년대 초반 2.5Gbps급 광통신 상용 시스템에서 10 Gbps 광통신 시스템 시험운영 단계를 지나, 21세기의 정보처리 수요를 해결하기 위해 파장다중(WDM; Wavelength Division Multiplexing) 광통신을 이용한 THz급 광통신 시스템 및 이에 관련된 소자의 연구를 필요로 하고 있다. (중략)

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.951-952
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• 2009

The long way toward new silicon technology, processed at very low temperature on any substrate, is described. The technology is based on CMIS (Complementary Metal Insulator Semiconductor) structure that shown its efficiency with known CMOS electronics. Present performance of this new technology is discussed through electrical parameters and reliability of transistors.