• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.565-568
• /
• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

• Journal of the Korean Society for Precision Engineering
• /
• v.30 no.1
• /
• pp.128-133
• /
• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.250-253
• /
• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.2
• /
• pp.6-12
• /
• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.241-241
• /
• 2009

For the Radio Frequency Integrated Passive Device (RFIPD) application, we have successfully developed and characterized high break-down voltage metal-insulator-metal (MIM) capacitors with 2,000 ${\AA}$ plasma-enhanced chemical vapor deposition (PECVD) silicon nitride which deposited with $SiH_4/NH_3$ gas mixing rate, working pressure, and RF power of PECVD at $250^{\circ}C$ chamber temperature. At the PECVD process condition of gas mixing rate (0.957), working pressure (0.9 Torr), and RF power (60 W), the AFM RMS value of about 2,000 ${\AA}$ silicon nitride on the bottom metal was the lowest of 0.862 nm and break-down electric field was the highest of about 8.0 MV/cm with the capacitance density of 326.5 $pF/mm^2$.

• Journal of Sensor Science and Technology
• /
• v.16 no.2
• /
• pp.126-131
• /
• 2007

In this paper, we fabricated piezoresistive pressure sensor with dry etching technology which used ICP-RIE (inductively coupled plasma reactive ion etching) and etching delay technology which used SOI (silicon-on-insulator). Structure of the fabricated pressure sensor shows a square diaphragm connected to a frame which was vertically fabricated by dry etching process and a single-element four-terminal gauge arranged at diaphragm edge. Sensitivity of the fabricated sensor was about 3.5 mV/V kPa at 1 kPa full-scale. Measurable resolution of the sensor was not exceeding 20 Pa. The nonlinearity of the fabricated pressure sensor was less than 0.5 %F.S.O. at 1 kPa full-scale.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.367-367
• /
• 2010

Electrical characteristics of Large-grain silicon with Ni-induced crystallization which gate insulator is made of 80 nm $SiO_2$ and 20 nm SiNx was fabricated and measured with different channel widths, channel length fixed $10{\mu}m$. Focusing on the changes of channel widths from $4{\mu}m$ to $40{\mu}m$. Field-effect mobility decreased from 111.30 to $94.10\;cm^2/V_s$ when the channel widths increased. Still threshold voltage was almost similar with -1.06V.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.15-16
• /
• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• Proceedings of the KIEE Conference
• /
• 2003.07c
• /
• pp.1912-1913
• /
• 2003

This paper presents a variable optical attenuator (VOA) that is fabricated using bosch deep silicon etching process [1] with silicon-on- insulator (SOI) wafer. The VOA consists of driving electrode, ground electrode, actuating mirror, and mechanical slower. In this VOA, actuating mirror is driven by electrostatic force [2] and the pull-in voltage is close to 13V, 28 V, 46V come along with the spring width of $3{\mu}m,\;5{\mu}m,\;7{\mu}m$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.9-16
• /
• 2008

In this paper, a simple analytical model for deriving the threshold voltage of a short-gate SOI MESFET is suggested. Using the iteration method, the Poisson equation in the fully depleted silicon channel and the Laplace equation in the buried oxide region are solved two-dimensionally, Obtained potential distributions in each region are expressed in terms of fifth-order of $\chi$, where $\chi$ denotes the coordinate perpendicular to the silicon channel direction. From them, the bottom channel potential is used to describe the threshold voltage in a closed-form. Simulation results show the dependencies of the threshold voltage on the various device geometry parameters and applied bias voltages.