• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.335-340
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• 2000

We investigated the role of the capping layers in the formation of the cobalt silicide in Co/Si systems with TiN and Ti capping layers and without capping layers. The Co/Si interfacial reactions and the phase transformations by the rapid thermal annealing (RTA) processes were observed by sheet resistance measurements, XRD, SIMS and TEM analyses for the clean silicon substrate as well as for the chemically oxidized silicon substrate by $H_2SO_4$. We observed the retardation of the cobalt disilicide formation in the Co/Si system with Ti capping layers. In the case of Co/$SiO_2$/Si system, cobalt silicide was formed by the Co/Si reaction due to with the dissociation of the oxide layer by the Ti capping layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.525-528
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• 2001

ZnO:Al thin film can be used as a transparent conducting oxide(TCO) which has low electric resistivity and high optical transmittance for the front electrode of amorphous silicon solar cells and display devices. This study of electrical, crystallographic and optical properties of Al doped ZnO thin films prepared by Facing Targets Sputtering(FTS), where strong internal magnets were contained in target holders to confine the plasma between the targets, is described. Optimal transmittance and resistivity was obtained by controlling flow rate of $O_2$ gas and substrate temperature. When the $O_2$ gas rate of 0.3 and substrate temperature $200^{\circ}C$, ZnO:Al thin film had strongly oriented c-axis and lower resistivity( < $10^{-4}{\Omega}-cm$ ).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.99-102
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• 2002

Pinholes on the thermally grown oxide, which is called gate oxide, on silicon substrate under polysilicon layer are found and its mechanism is analyzed in this paper. The oxide under a polysilicon layer is broken during the plasma etching process of other polysilicon layer. Both polysilicon layers are separated with 0.8${\mu}{\textrm}{m}$ thick oxide deposited by CVD (Chemical Vapor Deposition). Since broken oxide points are found scattered around an arc occurrence point, it is assumed that an extremely high electric field generated near the arc occurrence point makes the gate oxide broken. 1'he arc occurrence point has been observed on the alignment key and is the mark of low yield. It is found that any arc occurrence can cause chips to fail by breaking the gate oxide, even if are occurrence points are found on scribeline.

• Journal of the Korean institute of surface engineering
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• v.41 no.6
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• pp.331-334
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• 2008

The replica of highly ordered nano-sphere array patterns were fabricated using hot embossing method. First, silica nano-sphere array on Si substrate was transferred to PVC film at $130^{\circ}C$ and 7 bar using hot embossing process. Then, silica nano-sphere array on PVC template was removed by soaking the PVC film in buffered oxide etcher. In order to form anti-stiction layer, the PVC template was coated with silicon dioxide layer and self-assembled monolayer. Through UV nanoimprint lithography with the fabricated flexible PVC template, highly ordered nano-sphere array pattern was imprinted on curved substrates with high fidelity.

• ETRI Journal
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• v.26 no.4
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• pp.315-320
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• 2004

This paper proposes a 10-${\mu}m$ thick oxide layer structure that can be used as a substrate for RF circuits. The structure has been fabricated using an anodic reaction and complex oxidation, which is a combined process of low-temperature thermal oxidation (500 $^{\circ}C$ for 1 hr at $H_2O/O_2$) and a rapid thermal oxidation (RTO) process (1050 ${\circ}C$, for 1 min). The electrical characteristics of the oxidized porous silicon layer (OPSL) were almost the same as those of standard thermal silicon dioxide. The leakage current density through the OPSL of 10 ${\mu}m$ was about 10 to 50 $nA/cm^2$ in the range of 0 to 50 V. The average value of the breakdown field was about 3.9 MV/cm. From the X-ray photo-electron spectroscopy (XPS) analysis, surface and internal oxide films of OPSL prepared by a complex process were confirmed to be completely oxidized. The role of the RTO process was also important for the densification of the porous silicon layer (PSL) oxidized at a lower temperature. The measured working frequency of the coplanar waveguide (CPW) type short stub on an OPSL prepared by the complex oxidation process was 27.5 GHz, and the return loss was 4.2 dB, similar to that of the CPW-type short stub on an OPSL prepared at a temperature of 1050 $^{\circ}C$ (1 hr at $H_2O/O_2$). Also, the measured working frequency of the CPW-type open stub on an OPSL prepared by the complex oxidation process was 30.5 GHz, and the return was 15 dB at midband, similar to that of the CPW-type open stub on an OPSL prepared at a temperature of $1050^{\circ}C$ (1 hr at $H_2O/O_2$).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.5
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• pp.276-281
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• 2014

A high-responsive Schottky device has been achieved by forming a thin metal deposition on a Si substrate. Two-different metals of Ni and Ag were used as a Schottky metal contact with a thickness about 10 nm. The barrier height formation between metal and Si determines the rectifying current profiles. Ag-embedding Schottky device gave an extremely high response of 17,881 at a wavelength of 900 nm. An efficient design of Schottky device may applied for photoelectric devices, including photodetectors and solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.347-350
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• 2013

By inserting a very thin metal layer of Ag between two outer oxide layers of amorphous silicon indium zinc oxide (SIZO), we fabricated a highly transparent SIZO/Ag/SIZO multilayer on a glass substrate. In order to find the optimized thickness of Ag layers, we investigated the variation of optical properties depending on Ag thickness. It was found that the transition of Ag layer from island formation to a continuous film occurred at a critical thickness. Continuity of the Ag film is very important for optical properties in SIZO/Ag/SIZO multilayer. With about 15 nm thick Ag layer, the multilayer showed a high optical transmittance of 80% at 550 nm and low emissivity in IR.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.441-442
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• 2007

We deposited nickel oxide(NiO) thin films on silicon(Si) substrates at Room temperature and $500^{\circ}C$ using a nickel target by reactive DC and RF sputtering. In addition, we anneal to NiO thin films deposited at room temperature. Using spectroscopic eillipsometry, we obtained optical characteristics of every films. We discussed relations of the optical and structural properties of NiO thin films with the oxygen flow rate, substrate temperature and annealing temperatures. Refraction was decreased and defect was increased when NiO thin films was annealed. We also analyzed the electrical characteristics of NiO films which deposited DC and RF sputtering method.