• Title/Summary/Keyword: Silicon oxide nanowire

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Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

  • Pandian, M. Karthigai;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2079-2088
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    • 2014
  • In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong;Oh, Jae-Sub;Yun, Ho-Jin;Jeong, Kwang-Seok;Kim, Yu-Mi;Lee, Sang Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.3
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    • pp.139-142
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    • 2013
  • Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

  • Hong, Byoung-Hak;Lee, Seong-Joo;Hwang, Sung-Woo;Cho, Keun-Hwi;Yeo, Kyoung-Hwan;Kim, Dong-Won;Jin, Gyo-Young;Park, Dong-Gun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.2
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    • pp.80-87
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    • 2011
  • Low temperature hole transport characteristics of gate-all-around p-channel metal oxide semiconductor (PMOS) type silicon nanowire field-effect-transistors with the radius of 5 nm and lengths of 44-46 nm are presented. They show coexisting two single hole states randomly switching between each other. Analysis of Coulomb diamonds of these two switching states reveals a variety of electrostatic effects which is originated by the potential of a single hole captured in the trap near the nanowire.

Characteristics of Nanowire CMOS Inverter with Gate Overlap (Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구)

  • Yoo, Jeuk;Kim, Yoonjoong;Lim, Doohyeok;Kim, Sangsig
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.10
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    • pp.1494-1498
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    • 2017
  • In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

Size Scaling에 따른 Gate-All-Around Silicon Nanowire MOSFET의 특성 연구

  • Lee, Dae-Han;Jeong, U-Jin
    • Proceeding of EDISON Challenge
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    • 2014.03a
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    • pp.434-438
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    • 2014
  • CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

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Hydrogen sensing of Nano thin film and Nanowire structured cupric oxide deposited on SWNTs substrate: A comparison

  • Hoa, Nguyen Duc;Quy, Nguyen Van;O, Dong-Hun;Wei, Li;Jeong, Hyeok;Kim, Do-Jin
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2009.05a
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    • pp.52.1-52.1
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    • 2009
  • Cupric oxide (CuO) is a p-type semiconductor with band gap of ~1.7 eV and reported to be suitable for catalysis, lithium-copper oxide electrochemical cells, and gas sensors applications. The nanoparticles, plates and nanowires of CuO were found sensing to NO2, H2S and CO. In this work, we report about the comparison about hydrogen sensing of nano thin film and nanowires structured CuO deposited on single-walled carbon nanotubes (SWNTs). The thin film and nanowires are synthesized by deposition of Cu on different substrate followed by oxidation process. Nano thin films of CuO are deposited on thermally oxidized silicon substrate, whereas nanowires are synthesized by using a porous thin film of SWNTs as substrate. The hydrogen sensing properties of synthesized materials are investigated. The results showed that nanowires cupric oxide deposited on SWNTs showed higher sensitivity to hydrogen than those of nano thin film CuO did.

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Growth Characteristics of Amorphous Silicon Oxide Nanowires Synthesized via Annealing of Ni/SiO2/Si Substrates

  • Cho, Kwon-Koo;Ha, Jong-Keun;Kim, Ki-Won;Ryu, Kwang-Sun;Kim, Hye-Sung
    • Bulletin of the Korean Chemical Society
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    • v.32 no.12
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    • pp.4371-4376
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    • 2011
  • In this work, we investigate the growth behavior of silicon oxide nanowires via a solid-liquid-solid process. Silicon oxide nanowires were synthesized at $1000^{\circ}C$ in an Ar and $H_2$ mixed gas. A pre-oxidized silicon wafer and a nickel film are used as the substrate and catalyst, respectively. We propose two distinctive growth modes for the silicon oxide nanowires that both act as a unique solid-liquid-solid growth process. We named the two growth mechanisms "grounded-growth" and "branched-growth" modes to characterize their unique solid-liquid-solid growth behavior. The two growth modes were classified by the generation site of the nanowires. The grounded-growth mode in which the grown nanowires are generated from the substrate and the branchedgrowth mode where the nanowires are grown from the side of the previously grown nanowires or at the metal catalyst drop attached at the tip of the nanowire stem.

Formation of Silica Nanowires by Using Silicon Oxide Films: Oxygen Effect (산화 실리콘 막을 이용한 실리카 나노 와이어의 형성 : 산소 효과)

  • Yoon, Jong-Hwan
    • New Physics: Sae Mulli
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    • v.68 no.11
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    • pp.1203-1207
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    • 2018
  • In this study, silica nanowires were formed using silicon oxide films with different oxygen contents, and their microstructure and physical properties were compared with those of silica nanowires formed using Si wafers. The silicon oxide films were fabricated by using a plasma-enhanced chemical vapor deposition method. Silica nanowires were formed by thermally annealing silicon oxide films coated with nickel films as a catalyst. In the case of silicon oxide films having an oxygen content of approximately 50 at.% or less, the formation mechanism, microstructure, and physical properties of the nanowires were not substantially different from those of the silicon wafer. In particular, the uniformity of the thickness showed better behavior in the silicon oxide films. These results imply that silicon oxide films can be used as an alternative for fabricating high-quality silica nanowires at low cost.

Intracellular Electrical Stimulation on PC-12 Cells through Vertical Nanowire Electrode

  • Kim, Hyungsuk;Kim, Ilsoo;Lee, Jaehyung;Lee, Hye-young;Lee, Eungjang;Jeong, Du-Won;Kim, Ju-Jin;Choi, Heon-Jin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.407-407
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    • 2014
  • Nanotechnology, especially vertically grown silicon nanowires, has gotten great attentions in biology due to characteristics of one dimensional nanostructure; controllable synthetic structure such as lengths, diameters, densities. Silicon nanowires are promising materials as nanoelectrodes due to their highly complementary metal-oxide-semiconductor (CMOS) - and bio-compatibility. Silicon nanowires are so intoxicated that are effective for bio molecular delivery and electrical stimulation. Vertical nanowires with integrated Au tips were fabricated for electrical intracellular interfacing with PC-12 cells. We have made synthesized two types of nanowire devices; one is multi-nanowires electrode for bio molecular sensing and electrical stimulation, and the other is single-nanowires electrode respectively. Here, we demonstrate that differentiation of Nerve Growth Factor (NGF) treated PC-12 cells can be promoted depending on different magnitudes of electrical stimulation and density of Si NWs. It was fabricated by both bottom-up and top-down approaches using low pressure chemical vapor deposition (LPCVD) with high vacuuming environment to electrically stimulate PC-12 cells. The effects of electrical stimulation with NGF on the morphological differentiation are observed by Scanning Electron Microscopy (SEM), and it induces neural outgrowth. Moreover, the cell cytosol can be dyed selectively depending on the degree of differentiation along with fluorescence microscopy measurement. Vertically grown silicon nanowires have further expected advantages in case of single nanowire fabrication, and will be able to expand its characteristics to diverse applications.

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CO Gas Sensing Characteristic of ZnO Thin Film/Nanowire Based on p-type 4H-SiC Substrate at 300℃ (P형 4H-SiC 기판에 형성된 ZnO 박막/나노선 가스 센서의 300℃에서 CO 가스 감지 특성)

  • Kim, Ik-Ju;Oh, Byung-Hoon;Lee, Jung-Ho;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.2
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    • pp.91-95
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    • 2012
  • ZnO thin films were deposited on p-type 4H-SiC substrate by pulsed laser deposition. ZnO nanowires were formed on p-type 4H-SiC substrate by furnace. Ti/Au electrodes were deposited on ZnO thin film/SiC and ZnO nanowire/SiC structures, respectively. Structural and crystallographical properties of the fabricated ZnO thin film/SiC and ZnO nanowire/SiC structures were investigated by field emission scanning electron microscope and X-ray diffraction. In this work, resistance and sensitivity of ZnO thin film/SiC gas sensor and ZnO nanowire/SiC gas sensor were measured at $300^{\circ}C$ with various CO gas concentrations (0%, 90%, 70%, and 50%). Resistance of gas sensor decreases at CO gas atmosphere. Sensitivity of ZnO nanowire/SiC gas sensor is twice as big as sensitivity of ZnO thin film/SiC gas sensor.