• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• Journal of Ceramic Processing Research
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• v.13 no.spc2
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• pp.336-340
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• 2012

Wide band gap p-type hydrogenated amorphous silicon oxide (a-SiO:H) buffer layer has been used at the interface of transparent conductive oxide (TCO) and hydrogenated amorphous silicon (a-Si:H) p-type layer of a p-i-n type a-Si:H solar cell. Introduction of 5 nm thick buffer layer improves in blue response of the cell along with 0.5% enhancement of photovoltaic conversion efficiency (η). The cells with buffer layer show higher open circuit voltage (Voc), fill factor (FF), short circuit current density (Jsc) and improved blue response with respect to the cell without buffer layer.

• Journal of radiological science and technology
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• v.46 no.3
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• pp.187-195
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• 2023

A shield was made by mixing materials such as bismuth(Bi) and barium(Ba) with silicon to evaluate its shielding ability. Bismuth was made into a shield by mixing a bismuth oxide(Bi₂O₃) colloidal solution and a silicon base and applied to a fibrous fabric, and barium was made by mixing lead oxide(PbO) and barium sulfate(BaSO₄) with a silicon curing agent and solidifying it to make a shield. The test was conducted according to the lead equivalent test method for X-ray protective products of the Korean Industrial Standard. The experiment was conducted by increasing the shielding body one by one from the test condition of 60 kVp, 200 mA, 0.1sec and 100 kVp, 200 mA, 0.1 sec. At 60 kVp, 2 lead oxide-barium sulfate shields, 2 bismuth oxide 1.5 mm shields, and 5 bismuth oxide 0.3 mm shields showed shielding ability equal to or higher than that of lead 0.5 mm. At 100 kVp, 2 lead oxide-barium sulfate shields and 2 bismuth oxide 1.5 mm shields showed shielding ability equal to or higher than that of lead 0.5 mm. It was confirmed that when using 2 pieces of lead oxide-barium sulfate and 1.5 mm of bismuth oxide, respectively, it has shielding ability equivalent to that of lead. Bismuth oxide and lead oxide-barium sulfate are lightweight and have excellent shielding ability, thus they have excellent properties to be used as an apron for radiation protection or other shielding materials.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.699-704
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• 2018

One-dimensional nanostructures have attracted increasing attention because of their unique electronic, optical, optoelectrical, and electrochemical properties on account of their large surface-to-volume ratio and quantum confinement effect. Vertically grown nanowires have a large surface-to-volume ratio. The vapor-liquid-solid (VLS) process has attracted considerable attention for its self-alignment capability during the growth of nanostructures. In this study, vertically aligned silicon oxide nano-pillars were grown on Si\$SiO_2$(300 nm)\Pt substrates using two-zone thermal chemical vapor deposition system via the VLS process. The morphology and crystallographic properties of the grown silicon oxide nano-pillars were investigated by field emission scanning electron microscopy and transmission electron microscopy. The diameter and length of the grown silicon oxide nano-pillars were found to be dependent on the catalyst films. The body of the silicon oxide nano-pillars exhibited an amorphous phase, which is consisted with Si and O. The head of the silicon oxide nano-pillars was a crystalline phase, which is consisted with Si, O, Pt, and Ti. The vertical alignment of the silicon oxide nano-pillars was attributed to the preferred crystalline orientation of the catalyst Pt/Ti alloy. The vertically aligned silicon oxide nano-pillars are expected to be applied as a functional nano-material.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.4
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• pp.1033-1040
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• 1995

To simulate strength reliability and durability of ceramic parts under gas turbine application environments, particle impact damage behaviors in silicon carbide oxidized at 1673 K and 1523 K for 200 hours in atmosphere were investigated. The long-term oxidation produced a slight increase in the static fracture strength. Particle impact caused a spalling of oxide layer. The patterns of spalling and damage induced were dependent upon the property and impact velocity of the particle. Especially, the difference in spalling behaviors induced could be explained by introducing the formation mechanism of lateral crack and elastic-plastic deformation behavior at impact sit. At the low impact velocity regions, the oxidized SiC showed a little increase in the residual strength due to the cushion effect of oxide layer, as compared with the as-received SiC without oxide layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.223-224
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• 2008

Important element are low cost, high-efficiency crystalline silicon solar cells. in this paper, Will be able to contribute in low cost, high-efficiency silicon solar cells, Applies oxide/nitride passivation, produced screen-printed solar cells. and the Measures efficiency, and evaluated a justice quality oxide/nitride passivation screen-printed solar cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.31-36
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• 2004

we developed a technique to manufacture more reliable polycrystalline silicon TFT-LCDs using UV cleaning and buffered oxide etch(BOE) cleaning which remove the native oxide of the silicon surface before laser annealing. To investigate the effects of pre-treatments on the surface roughness of polycrystalline silicon, we measured atomic force microscopy(AFM). Also the electrical characteristics of polysilicon TFTs, breakdown characteristic and switching Performance, were tested for various pre-treatment conditions and several locations in large glass substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.334-338
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• 2006

Poly silicon TFT requires high quality dielectric film; conventional method of growing silicon dioxide needs highly hazardous chemicals such as silane. We have grown high quality dielectric film of silicon dioxide using non-hazardous chemical such as TFOS and ozone as reaction gases by APCVD. The films grown were characterized through C-V curves of MOS structures. Conventional APCVD requires high temperature processing where as in the process of current study, we developed a low temperature process. Interface trap density was substantially decreased in the silicon surface coated with the silicon dioxide film after annealing in nitrogen ambient. The interface with such low trap density could be used for poly silicon TFT fabrication with cheaper cost and potentially less hazards.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.59-63
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• 2015

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.