• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2021.11a
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• pp.6-7
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• 2021

Although the development of free-form architectural technology continues, it consumes a lot of money and time due to the one-time formwork and the difficulty of maintaining quality due to manual work. To this end, in this study, a shape connection technique was proposed and verified to improve the limitations of implementing the curved surface of the existing lower multi-point press. In order to improve the accuracy of the shape, a curved surface was implemented using a silicon cap and a silicon plate. As a result of the error analysis of the shape, a small value of less than 3 mm was found. This study can implement more accurate curved surfaces than conventional technologies and produce high-quality free-form panels.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.13 no.1
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• pp.107-114
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• 2014

A friction hinge system which moves without power was designed and developed using the principle of friction force, which is caused by interference between the inner diameter of a silicon cap and the outer diameter of a cylindrical roller bearing with one-way rotation in a counterclockwise direction. The system was applied to the lid of buffet ware, which moved up by external force and moved down by gravitational force. However, design conditions which included a rotation angle of the hinge of more than 80 degrees and a closing time of more than 20 seconds were required when the lid of the buffet ware closed due to gravitational force. The design safety of the friction hinge body connected to the lid of the buffet ware from the hinge system was checked on the basis of structural, fatigue and thermal analyses. The material of the shaft, cap and flange among the hinge elements was changed to polyethylene from steel to reduce the weight of the friction hinge system. An injection molding simulation was performed and injection molds of the shaft, cap and flange were created. The weight of the hinge system was decreased from 805g to 219g.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.818-824
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• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.17 no.2
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• pp.37-46
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• 2018

Present research is to evaluate and improve the sealing performance of the duct cap assembly for the ice dispensers through structural analysis. The nonlinear contact problems to check the sealing performance were analyzed using ANSYS software. The results of the analyses related to the sealing performance: the displacement distribution, the contact condition between the cap-silicon and the case, and the pressure distribution on the contact surface, were examined and discussed. Based on the results of the existing design of the duct cap assembly, two cases of the design modifications to improve the sealing performance were introduced. By examining the results of the two cases, a final design improvement plan was proposed and analyzed. It is shown that the sealing performance of the proposed final design is much more favorable than the existing design. The method of structural analysis and design improvement of the duct cap assembly presented in this paper will help improve the sealing performance of the ice dispenser duct caps.

• Applied Chemistry for Engineering
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• v.2 no.4
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• pp.393-398
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• 1991

An experimental reactor system was devised and employed to examine catalytic coal gasification. A 4-kw tungsten halogen lamp heater combinded with a graphite sample basket coated with silicon nitride film made rapid heating and cooling possible. Also a small graphite cap on the thermocouple tip which located just beneath the sample basket helped remarkably to read real temperatures. Silicon nitride film on the basket and the cap showed very good protection against the reaction between graphite and oxidant gases during the experiments. The weight of specimen could be continuously measured without disturbance.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Current Applied Physics
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• v.18 no.11
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• pp.1230-1234
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• 2018

We report a new method of measuring the non-radiative recombination rate in bulk Silicon. Synchrotron timeresolved x-ray scattering (TRXS) combines femtometer spatial sensitivity with nanosecond time resolution to record the temporal evolution of a crystal lattice following intense ultrafast laser excitation. Modeling this data requires an Auger recombination time that is considerably slower than previous measurements, which were made at lower laser intensities while probing only a relatively shallow surface depth. We attribute this difference to an enhanced Coulomb interaction that has been predicted to occur in bulk materials with high densities of photoexcited charge carriers.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.1-6
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• 2000

The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.275-278
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• 1999

We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD using $C_2$H$_2$gas. Since the discovery of carbon nanotubes, Synthesis of carbon nanotubes for mass production has been achieved by several methods such as laser vaporization, arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is of technological importance for applications to FED. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD. Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. Despite such breakthroughs in the growth, the growth mechanism of the alignment are still far from being clearly understood. Furthermore, FED has not been clearly demonstrated yet at a practical level. Here, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and then nanotubes are further grown by the cap growth mechanism.