• 제목/요약/키워드: Silicon Oxide Etching

검색결과 119건 처리시간 0.023초

양질의 FRO(fully recessed oxide)의 선택적 형성 (A selective formation of high-quality fully recessed oxide)

  • 류창우;심준환;이준희;이종현
    • 전자공학회논문지A
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    • 제33A권7호
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    • pp.149-155
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    • 1996
  • A new technique wasdeveloped which obtains selectively the htick fully recessed oxidized porous silicon layer (OPSL) with good dielectric property. The porous silicon layer was ocnverted to thick fully recessed oxide (FRO) with 3-step (1${\mu}$m, 1.5${\mu}$m, 1.8${\mu}$m) by multi-step thermal oxidation (after 400$^{\circ}$C, 1 hour by dry oxidation, 700$^{\circ}$C, 1 hour and then 1100$^{\circ}$C, 1 hour by wet oxidation). The breakdwon field of the FRO was about 2.5MV/cm and the leakage current was several pA ~ 100 pA in the range of 0 of 90 pF. The progress of oxidation of a porous silicon layer was studied by examining the infrared abosrption spectra. The refractive index (1.51) of the fRO, which was measured by ellipsometer, was comparable to that of the thermally grown silicon dioxide (1.46). The etching rate (1600${\AA}$/min) of the FRO was also almost equal to that of the thermal oxide.

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이산화실리콘 층의 예각부식 (Acute Angle Etching of silicon Dioxide Layer)

  • 최연익
    • 대한전자공학회논문지
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    • 제22권4호
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    • pp.84-91
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    • 1985
  • 열적으로 성장된 이산화실리콘 층 위에 실리카 필름 박막을 도포함으로써, 열산화막의 예각부식 공정이 제안되었다. 실리카필름의 밀화온도를 175$^{\circ}C$ 에서 1,150$^{\circ}C$로 변화시킴에 따라, $3^{\circ}$ 에서 $40^{\circ}$사이의 경사각을 얻었다. 또한 예각부식 공정의 해석적인 모형이 제시되었으며, 이산화실리콘 층의 부식단면을 기술하는 방정식이 Fermat의 최단시간 정리를 이용하여 유도되었다. 전자주사 현미경으로 부터 얻어진 부식단면과 이론적으로 계산된 단면을 비교한 결과, 서로 잘 부합되었다.

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Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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    • pp.79-79
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    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

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무수 불화수소와 메탄올의 기상식각에 의한 실리콘 표면 미세 가공 (Silicon Surface Micro-machining by Anhydrous HF Gas-phase Etching with Methanol)

  • 장원익;최창억;이창승;홍윤식;이종현;백종태;김보우
    • 센서학회지
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    • 제7권1호
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    • pp.73-82
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    • 1998
  • 실리콘 표면 미세가공에 있어서, 새로 개발된 HF 기상식각 공정은 미소구조체들을 띄우는데 매우 효과적임을 입증하였다. 무수 불화수소와 메탄올을 이용한 기상식각 시스템에 대한 기능 및 특성을 기술하였고, 실리콘 미세구조체룰 띄우기 위한 회생층 산화막들의 선택적 식각특성이 고찰되었다. 구조체층으로는 인이 주입된 다결정실리콘이나 SOI 기판의 단결정실리콘을 사용하였다. 회생층으로는 TEOS 산화막, 열산화막, 저온산화막을 사용하였다. 기존 습식식각과 비교해 볼 때, 공정에 기인된 고착현강이나 잔류물질이 없는 미세구조체를 성공적으로 제작하였다.

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플라즈마 에칭 후 게이트 산화막의 파괴 (Pinholes on Oxide under Polysilicon Layer after Plasma Etching)

  • 최영식
    • 한국정보통신학회논문지
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    • 제6권1호
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    • pp.99-102
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    • 2002
  • 다결정 실리콘층 아래의, 게이트 산화막이라고 불리는 높은 온도에서 형성된 산화막에서 핀홀이 관찰되었으며 그 메카니즘이 분석되었다. 다결정 실리콘층 아래의 산화막은 다른 다결정 실리콘층의 플라즈마 에칭 과정 동안에 파괴되어진다. 두 개의 다결정 실리콘층은 CVD증착에 의해 만들어진 0.8$\mu\textrm{m}$의 두꺼운 산화막에 의해 분리되어 있다. 파괴된 산화막들이 아크가 발생한 부분을 중심으로 흩어져 있으며 아크가 발생한 부분에서 생성된 극도로 강한 전계가 게이트 산화막을 파괴 시켰다고 가정된다. 아크가 발생한 부분은 Alignment key에서 관찰되었고 그리고 이것이 발견된 웨이퍼는 낮은 수율을 보여주었다. 아크가 발생한 부분이 칩의 내부가 아니더라도 게이트 산화막의 파괴에 의해 칩이 정상적으로 동작하지 않았다.

Potential Dependence of Electrochemical Etching Reaction of Si(111) Surface in a Fluoride Solution Studied by Electrochemical and Scanning Tunneling Microscopic Techniques

  • Bae, Sang-Eun;Youn, Young-Sang;Lee, Chi-Woo
    • Journal of Electrochemical Science and Technology
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    • 제11권4호
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    • pp.330-335
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    • 2020
  • Silicon surface nanostructures, which can be easily prepared by electrochemical etching, have attracted considerable attention because of its useful physical properties that facilitate application in diverse fields. In this work, electrochemical and electrochemical-scanning tunneling microscopic (EC-STM) techniques were employed to study the evolution of surface morphology during the electrochemical etching of Si(111)-H in a fluoride solution. The results exhibited that silicon oxide of the Si(111) surface was entirely stripped and then the surface became hydrogen terminated, atomically flat, and anisotropic in the fluoride solution during chemical etching. At the potential more negative than the flat band one, the surface had a tendency to be eroded very slowly, whereas the steps of the terrace were not only etched quickly but the triangular pits also deepened on anodic potentials. These results provided information on the conditions required for the preparation of porous nanostructures on the Si(111) surface, which may be applicable for sensor (or device) preparation (Nanotechnology and Functional Materials for Engineers, Elsevier 2017, pp. 67-91).

기상성장에 의한 Si단결정과 Si산화막의 특성( 1 ) (The Physical Properties of Silicon and Silicon-Oxide by Epitaxial Growth (1))

  • 성영권;오석주;김석기;이상수
    • 전기의세계
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    • 제22권2호
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    • pp.11-18
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    • 1973
  • This paper reports some results of Si and SiO$_{2}$ films obtained from the expitaxial growth by hydrogen reduction of SiCI$_{4}$ with a hydrogen and carbon dioxide mixture in an epitaxial-deposition chamber. The deposited Si and SiO$_{2}$ are studied by observing the process parameters affecting the rate of deposition, and the quantitative properties at the interface of Si and SiO$_{2}$ are also considered briefly according to the results of the optical absorption and the voltage-current characteristic of MOS etc. using step etching procedure for oxide films.

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Dendritic web으로 성장된 규소 결정속의 결함 규명 (Characterization of the structural defects in the dendritic web-grown silicon ribbon)

  • Kim, Young-Kwan
    • 한국결정성장학회지
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    • 제4권3호
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    • pp.276-283
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    • 1994
  • Dendritic-web 방법으로 성장된 규소의 결정속에 존재하는 여러 결합을 화학적 etching 방법으로 규명하였다. Twin plan상에 존재하는 전위의loop이 관찰되었고 이들은 규소의 self - interstital이 condensation되어서 형성된 것으로 판단된다. 이들 규소의 self-interstitial은 응고 온도로 부터의 급냉에 의하여 혹은 oxide precipitation에 의하여 생성되 것으로 여겨진다.

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실리콘 기판 위에 제작된 나노 크기의 구조물을 가진 그루브 표면이 이방성 젖음에 미치는 영향 (Effects of Grooved Surface with Nano-ridges on Silicon Substrate on Anisotropic Wettability)

  • 이동기;조영학
    • 한국생산제조학회지
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    • 제22권3_1spc호
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    • pp.544-550
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    • 2013
  • A grooved surface with anisotropic wettability was fabricated on a silicon substrate using photolithography, reactive ion etching, and a KOH etching process. The contact angles (CAs) of water droplets were measured and compared with the theoretical values in the Cassie state and Wenzel state. The experimental results showed that the contact area between a water droplet and a solid surface was important to determine the wettability of the water. The specimens with native oxide layers presented CAs ranging from $71.6^{\circ}$ to $86.4^{\circ}$. The droplets on the specimens with a native oxide layer could be in the Cassie state because they had relatively smooth surfaces. However, the CAs of the specimens with thick oxide layers ranged from $33.4^{\circ}$ to $59.1^{\circ}$. This indicated that the surface roughness for a specimen with a relatively thick oxide layer was higher, and the water droplet was in the Wenzel state. From the CA measurement results, it was observed that the wetting on the grooved surface was anisotropic for all of the specimens.

나노/마이크로 PDMS 채널 제작을 위한 마스크리스 실리콘 스템퍼 제작 및 레오로지 성형으로의 응용 (Maskless Fabrication of the Silicon Stamper for PDMS Nano/Micro Channel)

  • 윤성원;강충길
    • 소성∙가공
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    • 제13권4호
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    • pp.326-333
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    • 2004
  • The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.