• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• ETRI Journal
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• v.38 no.3
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• pp.455-462
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• 2016

Frequency hopping (FH) is a common characteristic of a wide variety of communication systems. On the other hand, software-defined radio (SDR) is an increasingly utilized technology for implementing modern communication systems. The main challenge when trying to realize an SDR FH system is the frequency tuning time, that is, the higher the hopping rate, the lower the required frequency tuning time. In this paper, significant universal hardware driver tuning options (within GNU Radio software) are investigated to discover the tuning option that gives the minimum frequency tuning time. This paper proposes an improved SDR frequency tuning algorithm for the generation of a target signal (with a given target frequency). The proposed algorithm aims to improve the frequency tuning time without any frequency deviation, thus allowing the realization of modern communication systems with higher FH rates. Moreover, it presents the design and implementation of an original GNU Radio Companion block that utilizes the proposed algorithm. The target SDR platform is that of the Universal Software Radio Peripheral USRP-N210 paired with the RFX2400 daughter board. Our results show that the proposed algorithm achieves higher hopping rates of up to 5,000 hops/second.

• ETRI Journal
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• v.31 no.1
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• pp.21-30
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• 2009

In low bit-rate video transmission, the payload of a single packet can often contain a whole coded frame due to the high compression ratio in both spatial and temporal domains of most modern video coders. Thus, the loss of a single packet not only causes the loss of a whole frame, but also produces error propagation into subsequent frames. In this paper, we propose a novel whole frame error concealment algorithm which reconstructs the first of the subsequent frames instead of the current lost frame to suppress the effects of error propagation. In the proposed algorithm, we impose a constraint which uses side match distortion (SMD) and overlapped region difference (ORD) to estimate motion vectors between the target reconstructed frame and its reference frame. SMD measures the spatial smoothness connection between a block and its neighboring blocks. ORD is defined as the difference between the correlated pixels which are predicted from one reference pixel. Experimental results show that the proposed algorithm effectively suppresses error propagation and significantly outperforms other conventional techniques in terms of both peak signal-to-noise ratio performance and subjective visual quality.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.10
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• pp.5056-5078
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• 2018

In this work we propose a compression technique that makes use of linear and perceptually uniform CIE $La^*b^*$ color space in the JPEG image compression framework to improve its performance at lower bitrates. To generate quantization matrices suitable for the linear and perceptually uniform CIE $La^*b^*$ color space, a novel linear Contrast Sensitivity Function (CSF) is used. The compression performance in terms of Compression Ratio (CR) and Peak Signal to Noise Ratio (PSNR), is further improved by utilizing image dependent, variable and non-uniform image sub-blocks generated using a proposed histogram-based merging technique. Experimental results indicate that the proposed linear CSF based quantization technique yields, on an average, 8% increase in CR for the same reconstructed image quality in terms of PSNR as compared to the conventional YCbCr color space. The proposed scheme also outperforms JPEG in terms of CR by an average of 45.01% for the same reconstructed image quality.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1081-1099
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• 2010

The TVM 430 system manufactured by Ansaldo STS in France is currently used in ground signalling system for Kyungbu HSR. It transmits the speed information to the on-board signalling system in the form of continuous signal via the track, and the rolling stock in Kyungbu HSR runs with 300km/h max. operating speed by using the corresponding information. Looking from the recent international trends in HSR, reducing the travelling time and increasing of the line capacity is promoting via the improvement of train speed. In case of TGV Est, they are realizing the normal operation with 320km/h max. operating speed by using TVM SEI signalling system, which is similar to TVM 430. Furthermore, in case Honam HSL, which is under construction, is looking over faster speed than the limited one of Kyungbu HSR(i.e. over 300km/h). In this paper, it is assumed that the existing TVM 430 ground signalling system is used and train speed is improved, therefore the number of block section to be increased depending on the increase of train speed and the standard speed to be used in this case is drawn via the simulation of the train model and described the method accordingly.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.3
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• pp.39-45
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• 2002

A simple and low cost stylus profiler made of ferrite cores is developed. The devised profiler consists of a contact probe, a measuring transducer, a signal processing unit, and a motorized stage. The contact probe attached to 4-bar spring maintains sufficient stiffness to protect disturbances. An overlap-area type inductive position sensing system is selected as a measuring transducer, which has high sensitivity, repeatability and linearity. The transducer is composed of coil bundles and ferrite cores which have good electromagnetic characteristics in spite of low cost. The repeatability of the profiler with the proposed inductive sensing system is better than 50nm. Experimental results are shown that the proposed profiler can measure the line or 3D profile of an object with sub-micron features.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.280-285
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• 2015

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.318-325
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• 2008

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2S
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• pp.701-710
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• 2000

This paper presents a new method for an efficient coding of very low bit-rate color video based on adaptive wavelet transform. Our approach reveals that the coding process works more efficiently if the quantized wavelet coefficients are preprocessed by a mechanism exploiting the redundancies in the wavelet subband structure. Thus, we focuses optimized activity of coding part, and exhaustive overlapped block motion compensation is utilized to ensure coherency in motion compensated error frames, and raised cosine window is applied. The horizontal and vertical components of motion vectors are encoded separately using adaptive arithmetic coding while significant wavelet coefficients are encoded in bit-plane order using adaptive arithmetic coding. On average the proposed codec exceeds H.263 and ZTE in peak signal-to-noise ratio by as much as 2.07 and 1.38dB at 28 kbits, respectively. Fore entire sequence coding, 3DWCVC method is superior to H.263 and ZTE by 0.35 and 0.71dB on average, respectively.