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http://dx.doi.org/10.5573/JSTS.2008.8.4.318

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration  

Jang, Young-Chan (Postech, Dep. EE)
Bae, Jun-Hyun (Postech, Dep. EE)
Lee, Ho-Young (Samsung Electronics Co., Ltd.)
You, Yong-Sang (Samsung Electronics Co., Ltd.)
Kim, Jae-Whui (Samsung Electronics Co., Ltd.)
Sim, Jae-Yoon (Postech, Dep. EE)
Park, Hong-June (Postech, Dep. EE)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.8, no.4, 2008 , pp. 318-325 More about this Journal
Abstract
A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.
Keywords
Flash ADC; offset; reference calibration; voting;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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