• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2011년도 춘계학술대회
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• pp.329-330
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• 2011

This paper concerns to the acquisition of Global Positioning System L1 C/A coded signals. It specifically addresses the issues of acquiring very low power signals which are attenuated due to special circumstances such as indoor environment or forest canopy etc. The proposed post-processing algorithm applies modified signal folding coherent integration scheme on weak signal record. It dynamically compensates the doppler effect on the length of C/A code before integrating the signal power. Experimental results show effectiveness of the algorithm on weak GPS signals recorded in a real environment.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.1-8
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• 2009

본 논문에서는 일반적인 Folding 구조를 이용한 R-String Folding Block과 Second Folding Block을 제안하여 최대 500Msample/s로 동작하는 ADC를 설계하였다. 제안된 Folding ADC의 R-String Folding Block에서는 상위 4bit를 병렬로 처리하여 디지털 출력을 얻어내며, Second Folding Block에서는 하위 4bit를 새로운 pipeline 방식을 통해 디지털 출력을 얻어낸다. HSPICE 시뮬레이션 과정을 통해 ADC 동작을 확인하였으며 최대 샘플링 주파수인 500Msample/s로 동작할 경우의 평균 전력소모는 1.34mW로 매우 작음을 확인하였다. 램프입력을 인가하면서 디지털 출력이 변할 때의 입력전압을 측정하여 DNL과 INL을 구한 결과 DNL은 $-0.56LSB{\sim}0.49LSB$, INL은 $-0.94LSB{\sim}0.72LSB$의 특성을 나타내었다. 사용된 MOSFET 파라미터는 MOSIS에서 제공하는 $0.35{\mu}m$ 공정 파라미터이다.

• BMB Reports
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• 제32권6호
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• pp.521-528
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• 1999

The folding of recombinant hepatitis B virus X-protein (rHBx) solubilized from Escherichia coli inclusion bodies was investigated. By sequential dialysis of urea, rHBx was folded into its native structure, which was demonstrated by the efficacy of its transcriptional activation of the adenovirus major late promoter (MLP), fluorescence spectroscopy, and circular dichroism (CD) analysis. The decrease in CD values at 220 nm and a corresponding blue shift of the intrinsic fluorescence emission confirmed the ability of rHBx to refold in lower concentrations of urea, yielding the active protein. Equilibrium and kinetic studies of the refolding of rHBx were carried out by tryptophan fluorescence measurements. From the biphasic nature of the fluorescence curves, the existence of stable intermediate states in the renaturation process was inferred. Reverse phase-high performance liquid chromatography (RP-HPLC) analysis further demonstrated the existence of these intermediates and their apparent compactness.

• ETRI Journal
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• 제35권4호
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• 전자공학회논문지C
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• 제34C권6호
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• 대한전자공학회논문지SD
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• 제48권4호
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• pp.14-23
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• 2011

본 논문에서는 자체보정 벡터 발생기(Self-Calibrated Vector Generator)를 이용한 7-bit 2GSPS folding/interpolation A/D Converter (ADC)를 제안한다. 제안하는 ADC는 2GSPS 의 고속 변환에 적합한 상위 2-bit, 하위 5-bit 인 분할구조로 설계 되었으며, 각각의 folding/interpolation rate는 4와 8로 설정되었다. 최대 1GHz의 높은 입력신호를 처리하기 위해 cascade 구조의 preprocessing block을 적용하였으며, 전압 구동 방식 interpolation 기법을 적용하여 기준전압 생성 시 발생하는 추가적인 전력소모를 최소화하였다. 또한, 새로운 개념의 자체보정 벡터 발생기를 이용하여 device mismatch, 기생 저항 및 커패시턴스 등에 의한 offset error를 최소화하였다. 제안하는 ADC는 1.2V 0.13um 1-poly 7-metal CMOS 공정을 사용하여 설계 되었으며 calibration 회로를 포함한 유효 칩 면적은 2.5$mm^2$ 이다. 측정 결과 입력 주파수 9MHz, sampling 주파수 2GHz에서 39.49dB의 SNDR 특성을 보이며, calibration 회로의 작동결과 약 3dB 정도의 SNDR의 상승을 확인하였다.

• 대한전자공학회논문지SD
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• 제47권7호
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• pp.61-69
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• 2010

본 논문에서는 기존 폴딩 구조의 A/D 변환기(ADC)가 지닌 경계조건 비대칭 오차를 극복하기 위해 홀수개의 폴딩 블록을 사용한 1.2V 8b 800MSPS CMOS ADC를 제안한다. 제안하는 ADC는 저 전력소모를 위해 폴딩 구조에 저항열 인터폴레이션 기법을 적용하고, 높은 folding rate(FR=9)를 극복하기 위해 cascaded 폴딩 구조를 채택하였다. 특히 폴딩 ADC의 주된 문제인 아날로그 신호의 선형성 왜곡과 offset 오차 감소를 위해 홀수개의 폴딩 블록을 사용하는 신호처리 기법을 제안하였다. 또한 스위치를 사용한 ROM 구조의 인코더를 채택하여 $2^n$ 주기를 가지지 않는 디지털 코드를 일반적인 바이너리 코드로 출력하였다. 제안하는 ADC는 $0.13{\mu}m$ 1P6M CMOS 공정을 사용하여 설계되었으며, 유효면적은 870um$\times$980um이다. 입력주파수 10MHz, 800MHz의 변환속도에서 150mW의 낮은 전력소모 특성을 보이며 SNDR은 44.84dB (ENOB 7.15bit), SFDR은 52.17dB의 측정결과를 확인하였다.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1985년도 학술발표회 논문집
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• pp.79-86
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• 1985

Residual-ecited linear prediction vocoding is known to be one of the best approaches to speech coding in the range of 4.8 to 9.6 kbits/s. One problem associated with the RELP vocoder is that it often produces some roughness and tonal noise as the transmission rate becomes lower. In this paper, we investigate three methods to improve its quality. These include the multiband spectral folding method, the method of using both the spectrally folded signal and the pulsed ecitation signal, and the method of using both the multiband spectrally folded signal and the pulsed ecitation signal. It has been found that, among the three methods, the last one yields the best performance. It produces no roughness and little tonal noise.

• 미생물학회지
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• 제29권5호
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• pp.270-277
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• 1991

A mutational alteration in the signal sequence of ribose-binding protein (RBP) of Escherichia coli, rbsB103, completely blocks the export of the protein to the periplasm. Intragenic suppressors for this mutation have been selected on minimal medium with ribose as a sole carbon source. Six suppressor mutations were characterized in detail and were found to have single amino acid wubstitution in the mature portion of RBP, which resulted in the mobility shift of the proteins on SDS polyacrylamide gel. Amino acid changes of these suppressors were localized in several peptides which are packed to form the N terminal domain of typical bilobate conformation of RBP. The involvement of SecB, a molecular chaperone, was investigated in the suppression of signal sequence mutation. Translocation efficency was found to be increased by the presence of SecB for all suppressors. It is likely that the folding characteristics of RBP altered by the suppressor mutations affect the affinity of interaction between SecB and RBP.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1994년도 FIFTH WESTERN PACIFIC REGIONAL ACOUSTICS CONFERENCE SEOUL KOREA
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.