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An 1.2V 8-bit 800MSPS CMOS A/D Converter with an Odd Number of Folding Block  

Lee, Dong-Heon (Department of Semiconductor Science, Dongguk University)
Moon, Jun-Ho (Department of Semiconductor Science, Dongguk University)
Song, Min-Kyu (Department of Semiconductor Science, Dongguk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.7, 2010 , pp. 61-69 More about this Journal
Abstract
In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.
Keywords
ADC; Odd number of Folding Block; Interpolation; Cascaded-folding; ROM encoder;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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