• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2011.06a
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• pp.329-330
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• 2011

This paper concerns to the acquisition of Global Positioning System L1 C/A coded signals. It specifically addresses the issues of acquiring very low power signals which are attenuated due to special circumstances such as indoor environment or forest canopy etc. The proposed post-processing algorithm applies modified signal folding coherent integration scheme on weak signal record. It dynamically compensates the doppler effect on the length of C/A code before integrating the signal power. Experimental results show effectiveness of the algorithm on weak GPS signals recorded in a real environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• BMB Reports
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• v.32 no.6
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• pp.521-528
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• 1999

The folding of recombinant hepatitis B virus X-protein (rHBx) solubilized from Escherichia coli inclusion bodies was investigated. By sequential dialysis of urea, rHBx was folded into its native structure, which was demonstrated by the efficacy of its transcriptional activation of the adenovirus major late promoter (MLP), fluorescence spectroscopy, and circular dichroism (CD) analysis. The decrease in CD values at 220 nm and a corresponding blue shift of the intrinsic fluorescence emission confirmed the ability of rHBx to refold in lower concentrations of urea, yielding the active protein. Equilibrium and kinetic studies of the refolding of rHBx were carried out by tryptophan fluorescence measurements. From the biphasic nature of the fluorescence curves, the existence of stable intermediate states in the renaturation process was inferred. Reverse phase-high performance liquid chromatography (RP-HPLC) analysis further demonstrated the existence of these intermediates and their apparent compactness.

• ETRI Journal
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• v.35 no.4
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• Proceedings of the Acoustical Society of Korea Conference
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• 1985.10a
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• pp.79-86
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• 1985

Residual-ecited linear prediction vocoding is known to be one of the best approaches to speech coding in the range of 4.8 to 9.6 kbits/s. One problem associated with the RELP vocoder is that it often produces some roughness and tonal noise as the transmission rate becomes lower. In this paper, we investigate three methods to improve its quality. These include the multiband spectral folding method, the method of using both the spectrally folded signal and the pulsed ecitation signal, and the method of using both the multiband spectrally folded signal and the pulsed ecitation signal. It has been found that, among the three methods, the last one yields the best performance. It produces no roughness and little tonal noise.

• Korean Journal of Microbiology
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• v.29 no.5
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• pp.270-277
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• 1991

A mutational alteration in the signal sequence of ribose-binding protein (RBP) of Escherichia coli, rbsB103, completely blocks the export of the protein to the periplasm. Intragenic suppressors for this mutation have been selected on minimal medium with ribose as a sole carbon source. Six suppressor mutations were characterized in detail and were found to have single amino acid wubstitution in the mature portion of RBP, which resulted in the mobility shift of the proteins on SDS polyacrylamide gel. Amino acid changes of these suppressors were localized in several peptides which are packed to form the N terminal domain of typical bilobate conformation of RBP. The involvement of SecB, a molecular chaperone, was investigated in the suppression of signal sequence mutation. Translocation efficency was found to be increased by the presence of SecB for all suppressors. It is likely that the folding characteristics of RBP altered by the suppressor mutations affect the affinity of interaction between SecB and RBP.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.