• Journal of the Korean Ceramic Society
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• v.37 no.4
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• pp.359-367
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• 2000

Particulate composites of Al2O3/SiC, Al2O3/ZrO2 and Al2O3/ZrO2/SiC have been fabricated to investigate their R-curve behaviors and toughening mechanisms. Al2O3 containing 30 vol% SiC particles of 3${\mu}{\textrm}{m}$ showed rising R-curve behavior owing to the strong crack bridging by SiC particles. The fracture toughness reached 9.1 MPa {{{{ SQRT {m} }} at the crack length of 1000${\mu}{\textrm}{m}$. On the other hand, ZrO2-toughened Al2O3 had a high flat R-curve since it rose steeply in the short crack region due to the well known transformation toughening. For Al2O3/ZrO2/SiC composites, the R-curve behavior was similar to that of Al2O3/SiC but with slightly higher toughness. The SiC particles in this composite decreased the amount of transformable tetragonal phase to reduce the effect of transformation toughening by 50%. It was also found that the fracture toughness of this composite with two different toughening mechanisms was markedly lower than that estimated by the simple addition of two contributions.

• Journal of Ceramic Processing Research
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• v.13 no.spc2
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• pp.373-376
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• 2012

Thin films of Ag-SiO2-TiO2 composite oxides with SiO2/TiO2 of 20/80 molar compositions were prepared by the sol-gel method, using tetraethylorthosilicate (TEOS) and titanium isopropoxide (TIP) as precursors. Ag-SiO2-TiO2 films coated on commercial glass substrates have successfully been synthesized using sol-gel method. The Ag-SiO2-TiO2 film with 0.5% Ag-added concentration and 20 mol% SiO2-mixture gives optimal results on crystalline structure, optical property, surface area, and photochromic property. Absorption near the wavelength of the incident light decreased gradually. The reversibility of the two-photon writing process in Ag-SiO2-TiO2 film is clearly seen.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.44-47
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• 2012

The $TiO_2/Si_3N_4/Ag/Si_3N_4/TiO_2$ multi layered structure was designed for the possible application of transparent electrodes in PDP (Plasma Display Panel). Multi layered film was deposited on a glass substrate at room temperature by DC/RF magnetron sputtering system and EMP (Essential Macleod Program) was adopted to optimize the optical characteristics of film. During the deposition process, the Ag layer in $TiO_2/Ag/TiO_2$ became heavily oxidized and the filter characteristic was degraded easily. In thus study, Si3N4 layer was used as a diffusion buffer layer between $TiO_2$ and Ag. in order to prevent the oxidation of Ag layer in $TiO_2/Si_3N_4/Ag/Si_3N_4/TiO_2$ structure. It was confirmed that $Si_3N_4$ layer is one of candidate materials acting as diffusin barrier between $TiO_2/Ag/TiO_2$.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.130-137
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• 2008

$La_{0.7}Sr_{0.3}MnO_3$ films were deposited on $SiO_2$/Si and Si substrates annealed at $350^{\circ}C$ by rf magnetron sputtering. The oxygen gas flow rates were varied as 0, 40, and 80 sccm. Without post annealing process, $La_{0.7}Sr_{0.3}MnO_3$ thin films on $SiO_2$/Si and Si substrates were polycrystalline with (100), (110), and (200) growth planes. The grain size of $La_{0.7}Sr_{0.3}MnO_3$ thin films was increased with increasing oxygen gas flow rate. The sheet resistance of $La_{0.7}Sr_{0.3}MnO_3$ thin films was decreased with oxygen flow rate due to the increased grain size which induced a reduction of grain boundary. TCR (temperature coefficient of resistance) values of $La_{0.7}Sr_{0.3}MnO_3$ thin films were obtained from -2.0% to -2.2%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.625-630
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• 1987

Thermal evaporated SiO rf sputtered SiO2 thin films were most widely used to the gate oxide of TFTs. In this paper, the difference of trap density and distribution between SiO2 and SiO2 film were studied. TFTs using SiO and SiO2 thin film for the gate oxide were fabricated. The output characteirstics of TFTs and the time dpendencd of the leakage current were measured. Models of the carrier transport and carrier trapping in TFT were proposed. The trap density was obtained by substituting measured value for the equation derived from the proposed model. It was found that rf sputtered SiO2 had more traps at interface than thermal evaporated SiO.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• Journal of the Korean Chemical Society
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• v.44 no.1
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• pp.60-67
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• 2000

The wavelength of the surface plasmon absorption depends on the dielectric matrix. $TiO_2/SiO_2$ complex oxide films doped with Au nanoclusters were prepared by sol-gel spin-coating method using $Ti(OPr^i)_4$, $Si(OEt)_4$, and $HAuCl_4{\cdot}7H_2O$. The wavelength of the maximum absorption of Au nanoehrsters in the $TiO_2/SiO_2$ thin films was obtained with lineality from 540 nm to 615 nm depending on the molar ratio of $TiO_2$. The particle sizes and structures of these nanoclusters have been identified through a TEM and X-ray diffraction patterns. The dielectric constants of $TiO_2/SiO_2$ thin films were calculated from the experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.22-26
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• 2013

PTCR ceramics of $(Ba_{0.998}Sm_{0.002})TiO_3+0.001MnCO_3+xSiO_2$ (x=1, 2, 3, 4, 5, 6 mol%) were fabricated by solid state method. Disk samples of diameter 5 mm and thickness about 1mm were sintered at $1,290^{\circ}C$ for 2 h in reduced atmosphere of $5%H_2-95%N_2$ followed by re-oxidation at $600^{\circ}C$ for 30 min. in $20%O_2-80%N_2$.and their microstructures and electrical properties were investigated with SEM and Multimeter. The color of sintered samples was strongly dependent on $SiO_2$ content showing that the color of samples with $SiO_2$ of 1~2 mol% was gray but that of samples with $SiO_2$ of 4~6 mol% was changed from gray to blue, which seems to be related with the reduction of samples due to the oxygen vacancies created during the sintering in reduced atmosphere. $SiO_2$ content had a great influence on the microstructure and the electrical properties. With increasing $SiO_2$ content, the grain size of samples increased and the resistivity as well as the resistivity jump ($R_{285}/R_{min}$) decreased, which is considered to be attributed to the resistivity change at grain interior and grain boundary due to the fast mass transfer through $SiO_2$ liquide phase during the sintering. Samples with 2 mol% $SiO_2$ has the resistivity of $202{\Omega}cm$ and the resistivity jump of 3.28. It is expected that $SiO_2$ doped $BaTiO_3$ based PTC ceramics can be used for multilayered PTC thermistor due to the resistance to the sintering in reduced atmosphere.