• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.83-87
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• 2020

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga's figure of merit (~94.22 MW/㎠) than the symmetric structure (~46.93 MW/㎠), and the breakdown voltage of the device increases by approximately 70%.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.21-30
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• 2018

Driven by the recent energy saving trend, conventional silicon based power conversion modules are being replaced by modules using silicon carbide. Previous papers have focused mainly on the electrical advantages of silicon carbide semiconductors that can be used to design switching devices with much lower losses than conventional silicon based devices. However, no systematic study of their thermomechanical reliability in power conversion modules using finite element method (FEM) simulation has been presented. In this paper, silicon and silicon carbide based power devices with three-phase switching were designed and compared from the viewpoint of thermomechanical reliability. The switching loss of power conversion module was measured by the switching loss evaluation system and measured switching loss data was used for the thermal FEM simulation. Temperature and stress/strain distributions were analyzed. Finally, a thermal fatigue simulation was conducted to analyze the creep phenomenon of the joining materials. It was shown that at the working frequency of 20 kHz, the maximum temperature and stress of the power conversion module with SiC chips were reduced by 56% and 47%, respectively, compared with Si chips. In addition, the creep equivalent strain of joining material in SiC chip was reduced by 53% after thermal cycle, compared with the joining material in Si chip.

• Journal of Sensor Science and Technology
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• v.22 no.3
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• pp.175-180
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• 2013

This paper describes the characteristics of cubic silicon carbide (3C-SiC) films grown on a carbonized Si(100) substrate, using hexamethyldisilane (HMDS, $Si_2(CH_3)_6$) as a safe organosilane single precursor in a nonflammable $H_2$/Ar ($H_2$ in Ar) mixture carrier gas by atmospheric pressure chemical vapor deposition (APCVD) at $1280^{\circ}C$. The growth process was performed under various conditions to determine the optimized growth and carbonization condition. Under the optimized condition, grown film has a single crystalline 3C-SiC with well crystallinity, small voids, low residual stress, low carrier concentration, and low RMS. Therefore, the 3C-SiC film on the carbonized Si (100) substrate is suitable to power device and MEMS fields.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.49-54
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• 2017

In this paper, recent researches on new and renewable energy have been conducted due to problems such as energy exhaustion and environmental pollution, and new researches on high efficiency and high speed switching are needed. Therefore, we compared the efficiency by using high speed switching devices instead of IGBT which can't be used in high speed switching. The experiment was performed theoretically by applying the same parameters of the high speed switching devices which are the Cool MOS of Infineon Co., SiC C3M of Cree, and GaN FET device of Transform, by implementing the DC-DC boost converter and measuring the actual efficiency for output power and frequency. As a result, the GaN FET showed good efficiency at all switching frequency and output power.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.197-201
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• 2010

This paper describes the fabrication and characteristics of a NO sensor using ZnO thin film integrated 3C-SiC micro heater based on polycrystalline 3C-SiC thin film of operation in harsh environments. The sensitivity, response time, and operating properties in high temperature and voltages of NO sensors based SiC MEMS are measured and analyzed. The sensitivity of device with pure ZnO thin film at the heater operating power of 13.5 mW ($300^{\circ}C$) is 0.875 in NO gas concentration of 0.046 ppm. In the case of Pt doping, the sensitivity of at power consumption of 5.9 mW ($250^{\circ}C$) was 1.92 at same gas flow rate. The ZnO with doped Pt was showed higher sensitivity, lower working temperature and faster adsorption characteristics to NO gas than pure ZnO thin film. The NO gas sensor integrated SiC micro heater is more strength than others in high voltage and temperature environments.

• 전기의세계
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• v.63 no.5
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• pp.14-17
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• 2014

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.