• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.199-202
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• 2017

Silicon carbide (SiC) is being spotlighted as a next-generation power semiconductor material owing to the characteristic limitations of the existing silicon materials. SiC has a wider band gap, higher breakdown voltage, higher thermal conductivity, and higher saturation electron mobility than those of Si. When using this material to implement Schottky barrier diode (SBD) devices, SBD-state operation loss and switching loss can be greatly reduced as compared to that of traditional Si. However, actual SiC SBDs exhibit a lower dielectric breakdown voltage than the theoretical breakdown voltage that causes the electric field concentration, a phenomenon that occurs on the edge of the contact surface as in conventional power semiconductor devices. Therefore in order to obtain a high breakdown voltage, it is necessary to distribute the electric field concentration using the edge termination structure. In this paper, we designed an edge termination structure using a field plate structure through oxide etch angle control, and optimized the structure to obtain a high breakdown voltage. We designed the edge termination structure for a 650 V breakdown voltage using Sentaurus Workbench provided by IDEC. We conducted field plate experiments. under the following conditions: $15^{\circ}$, $30^{\circ}$, $45^{\circ}$, $60^{\circ}$, and $75^{\circ}$. The experimental results indicated that the oxide etch angle was $45^{\circ}$ when the breakdown voltage characteristics of the SiC SBD were optimized and a breakdown voltage of 681 V was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.409-412
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• 2004

Edge termination technique is essential fer the fabrication of high volage devices. A proper edge termination technique is also needed in the fabrication of Silicon Carbide power devices for obtaining a stable high blocking voltage properties. Among the many techniques, the field plate formation is the easiest one that can utilize it for commercial usage. The growth of thick thermal oxide is difficult for SiC, however. In this paper, 6A grade SiC schottky barrier diodes(SBD) were fabricated with field plate edge termination. The oxides which is field plate were formed various methods such as dry oxidation, 10% $N_2O$ nitrided oxidation and PECVD deposition. The reverse characteristics of the SiC SBD with various oxide field plate were investigated.

• Journal of IKEEE
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• v.24 no.2
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• pp.604-609
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• 2020

We investigated the influence of rapid thermal annealing on aluminum nitride (AlN) thin film Schottky barrier diodes (SBDs) manufactured structures deposited on a 4H-silicon carbide (SiC) wafer using radio frequency sputtering. The Ni/AlN/4H-SiC devices annealed at 400℃ exhibited Schottky barrier diode (SBDs) properties with an on/off current ratio that was approximately 10 times higher than that of the as-deposited device structures and the devices annealed at 600℃ as measured at room temperature. Auger electron spectroscopy (AES) measurements revealed that atomic oxygen concentrations in the annealed AlN devices at 400℃, is ascribed to the improvement in on/off ratio and the reduction of on-resistance. Additionally, we investigated the electrical characteristics of the AlN/SiC SBD structures depending on the frequency variation of sound waves.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.123-126
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• 2022

We investigated deep levels in n-type 4H-SiC epitaxy layer of the Positive-Intrinsic-Negative diode and Schottky barrier diodes by using deep level transient spectroscopy. Despite the excellent performance of 4H-SiC, research on various deep level defects still requires a lot of research to improve device performance. In Positive-Intrinsic-Negative diode, two defects of 196K and 628K are observed more than Schottky barrier diode. This is related to the action of impurity atoms infiltrating or occupying the 4H-SiC lattice in the ion implantation process. The I-V characteristics of the Positive-Intrinsic-Negative diode shows about ~100 times lower the leakage current level than Schottky barrier diode due to the grid structures in Positive-Intrinsic-Negative. As a result of comparing the capacitance of devices diode and Schottky barrier diode devices, it can be seen that the capacitance value lowered if it exists the P implantation regions from C-V characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.191-192
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• 2005

The reverse breakdown voltages of 4H-SiC SBD(schottky barrier diode)s with FP(Field Plate) and/or FLR(Field Limiting Ring) as a edge termination, were investigated. The breakdown voltages of SBDs with FP ware investigated varying the overlap width from $1{\mu}m$ to $30{\mu}m$. The maximum average breakdown voltages was 475V. There is no significant changes for the devices with overlap width of between $5{\mu}m\sim30{\mu}m$. It was confirmed that the dielectric breakdown of the thin thermal oxide is main cause of device failure. However, the breakdown voltage of SBD with FLR was 1400V even though the FLR edge termination structure was not optimized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.285-288
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• 2004

탄화규소 기판의 에피 박막결함으로는 dislocation, micropipe, pin-hole 및 에피층 표면의 여러 가지 결함들이 있다. 이러한 결함들이 탄화규소 쇼트키 다이오드의 항복전압과 어떠한 상관관계가 존재하는지 알아 보기 위해 탄화규소 쇼트키 다이오드를 제작하고, 제작된 소자의 항복전압을 측정하였다. 에피 박막내의 결함 분포를 알아보기 위해 항복전압 측정후 KOH 용액을 이용한 SiC의 에칭을 수행하였으며, 제작된 여러소자들에 대해 항복전압의 분포도와 결함 분포도를 작성, 비교 관찰하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.367-371
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• 2018

1,200 V class junction barrier schottky (JBS) diodes and schottky barrier diodes (SBD) were simultaneously fabricated on the same 4H-SiC wafer. The resulting diodes were characterized at temperatures from room temperature to 473 K and subsequently compared in terms of their respective I-V characteristics. The parameters deduced from the observed I-V measurements, including ideality factor and series resistance, indicate that, as the temperature increases, the threshold voltage decreases whereas the ideality factor and barrier height increase. As JBS diodes have both Schottky and PN junction structures, the proper depletion layer thickness, $R_{on}$, and electron mobility values must be determined in order to produce diodes with an effective barrier height. The comparison results showed that the JBS diodes exhibit a larger effective barrier height compared to the SBDs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.147-150
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• 2003

In this paper, We fabricated a high temperature pressure sensor using SBD(silicon- direct-bonding) wafer of $Si/SiO_2$/Si-sub structure. This sensor was very sensitive because the piezoresistor is fabricated by single crystal silicon of the first layer of SDB wafer. Also, it was possible to operate the sensor at high temperature over $120^{\circ}C$ which is the temperature limitation of general silicon sensor because the piezoresistor was dielectric isolation from silicon substrate using silicon dioxide of the second layer. The sensitivity of this sensor is very high as the measured result of D2200 shows $183.6\;{\mu}V/V{\cdot}kPa$. Also, the output characteristic of linearity was very good. This sensor was available at high temperature as $300^{\circ}C$.

• Journal of IKEEE
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• v.26 no.1
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• pp.50-55
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• 2022

SiC is a power semiconductor with a wide bandgap, high insulation failure strength, and thermal conductivity, but many deep-level defects. Defects that appear in SiC can be divided into two categories, defects that appear in physical properties and interface traps that appear at interfaces. In this paper, Z_1/2 trap concentration 0 ~ 9×10¹⁴ cm^-3 reported at room temperature (300 K) is applied to SiC substrates and epi layer to investigate turn-on characteristics. As the trap concentration increased, the current density, Shockley-read-Hall (SRH), and Auger recombination decreased, and Ron increased by about 550% from 0.004 to 0.022 mohm.