• Title/Summary/Keyword: SiC MOSFET

Search Result 164, Processing Time 0.024 seconds

Short-circuit Protection Circuit Design for SiC MOSFET Using Current Sensing Circuit Based on Rogowski Coil (Rogowski Coil 기반의 전류 센싱 회로를 적용한 SiC MOSFET 단락 보호 회로 설계)

  • Lee, Ju-A;Byun, Jongeun;Ann, Sangjoon;Son, Won-Jin;Lee, Byoung-Kuk
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.26 no.3
    • /
    • pp.214-221
    • /
    • 2021
  • SiC MOSFETs require a faster and more reliable short-circuit protection circuit than conventional methods due to narrow short-circuit withstand times. Therefore, this research proposes a short-circuit protection circuit using a current-sensing circuit based on Rogowski coil. The method of designing the current-sensing circuit, which is a component of the proposed circuit, is presented first. The integrator and input/output filter that compose the current-sensing circuit are designed to have a wide bandwidth for accurately measuring short-circuit currents with high di/dt. The precision of the designed sensing circuit is verified on a double pulse test (DPT). In addition, the sensing accuracy according to the bandwidth of the filters and the number of turns of the Rogowski coil is analyzed. Next, the entire short-circuit protection circuit with the current-sensing circuit is designed in consideration of the fast short-circuit shutdown time. To verify the performance of this circuit, a short-circuit test is conducted for two cases of short-circuit conditions that can occur in the half-bridge structure. Finally, the short-circuit shutdown time is measured to confirm the suitability of the proposed protection circuit for the SiC MOSFET short-circuit protection.

Performance of an SiC-MOSFET Based 11-kW Bi-directional On-board Charger (SiC-MOSFET 기반 11-kW급 양방향 탑재형 충전기 성능)

  • Lee, Sang-Youn;Lee, Woo-Seok;Lee, Jun-Young;Lee, Il-Oun
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.26 no.5
    • /
    • pp.376-379
    • /
    • 2021
  • The design and performance of a SiC-MOSFET-based 11-kW bi-directional on-board charger (OBC) for electric vehicles is presented. The OBC consists of a three-phase two-level AC/DC converter and a CLLLC resonant converter. All the power devices are implemented with SiC-MOSFETs to reduce the conduction losses generated in the OBC, and the DC-link voltage is designed to track the level of battery voltage in the forward and reverse powering modes. As a result, the CLLLC resonant converter always runs at the switching frequency near the resonant frequency, resulting in high-efficiency operation at the maximum powering modes. As the DC-link voltage varies according to the battery voltage, the AC/DC converter in the proposed OBC adopts an adaptive DC-link voltage controller. The performance of the proposed 11-kW OBC is verified by a prototype converter with the following specifications: three-phase 60-Hz 380-V input, 11-kW capacity, and battery voltage range of 214-413-V, resulting in the conversion efficiency of over 95.0-% in the forward and reverse powering modes.

An Improved Analytical Model for Predicting the Switching Performance of SiC MOSFETs

  • Liang, Mei;Zheng, Trillion Q.;Li, Yan
    • Journal of Power Electronics
    • /
    • v.16 no.1
    • /
    • pp.374-387
    • /
    • 2016
  • This paper derives an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of SiC MOSFETs. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of the trans-conductance. The turn-on process and the turn-off process are illustrated in detail, and equivalent circuits are derived and solved for each switching transition. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. Note that switching losses calculated based on experiments are imprecise, because the energy of the junction capacitances is not properly disposed. Finally, the proposed analytical model is utilized to account for the effects of parasitic elements on the switching performance of a SiC MOSFET, and the circuit design rules for high frequency circuits are given.

SiC/SiO2 Interface Characteristics in N-based 4H-SiC MOS Capacitor Fabricated with PECVD and NO Annealing Processes (PECVD와 NO 어닐링 공정을 이용하여 제작한 N-based 4H-SiC MOS Capacitor의 SiC/SiO2 계면 특성)

  • Song, Gwan-Hoon;Kim, Kwang-Soo
    • Journal of IKEEE
    • /
    • v.18 no.4
    • /
    • pp.447-455
    • /
    • 2014
  • In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

Optimization of 4H-SiC Vertical MOSFET by Current Spreading Layer and Doping Level of Epilayer (Current Spreading Layer와 에피 영역 도핑 농도에 따른 4H-SiC Vertical MOSFET 항복 전압 최적화)

  • Ahn, Jung-Joon;Moon, Kyoung-Sook;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.23 no.10
    • /
    • pp.767-770
    • /
    • 2010
  • In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

Thermal Design of High Power Semiconductor Using Insulated Metal Substrate (Insulated Metal Substrate를 사용한 고출력 전력 반도체 방열설계)

  • Bongmin Jeong;Aesun Oh;Sunae Kim;Gawon Lee;Hyuncheol Bae
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.30 no.1
    • /
    • pp.63-70
    • /
    • 2023
  • Today, the importance of power semiconductors continues to increase due to serious environmental pollution and the importance of energy. Particularly, SiC-MOSFET, which is one of the wide bandgap (WBG) devices, has excellent high voltage characteristics and is very important. However, since the electrical properties of SiC-MOSFET are heatsensitive, thermal management through a package is necessary. In this paper, we propose an insulated metal substrate (IMS) method rather than a direct bonded copper (DBC) substrate method used in conventional power semiconductors. IMS is easier to process than DBC and has a high coefficient of thermal expansion (CTE), which is excellent in terms of cost and reliability. Although the thermal conductivity of the dielectric film, which is an insulating layer of IMS, is low, the low thermal conductivity can be sufficiently overcome by allowing a process to be very thin. Electric-thermal co-simulation was carried out in this study to confirm this, and DBC substrate and IMS were manufactured and experimented for verification.

4H-SiC Curvature VDMOSFET with 3.3kV Breakdown Voltage (3.3kV 항복 전압을 갖는 4H-SiC Curvature VDMOSFET)

  • Kim, Tae-Hong;Jeong, Chung-Bu;Goh, Jin-Young;Kim, Kwang-Soo
    • Journal of IKEEE
    • /
    • v.22 no.4
    • /
    • pp.916-921
    • /
    • 2018
  • In this paper, we analyzed the power MOSFET devices for high voltage and high current operation. 4H-SiC was used instead of Si to improve the static characteristics of the device. Since 4H-SiC has a high critical electric field due to wide band gap, 4H-SiC is more advantageous than Si in high voltage and high current operation. In the conventional VDMOSFET structure using 4H-SiC, the breakdown voltage is limited due to the electric field crowding at the edge of the p-base region. Therefore, in this paper, we propose a Curvature VDMOSFET structure that improves the breakdown voltage and the static characteristics by reducing the electric field crowding by giving curvature to the edge of the p-base region. The static characteristics of conventional VDMOSFET and curvature VDMOSFET are compared and analyzed through TCAD simulation. The Curvature VDMOSFET has a breakdown voltage of 68.6% higher than that of the conventional structure without increasing on-resistance.

GaN E-HEMT for the next era of power conversion

  • Bailley, Charles
    • Proceedings of the KIPE Conference
    • /
    • 2017.07a
    • /
    • pp.564-576
    • /
    • 2017
  • ${\cdot}$ GaN E-HEMT provides superior performance vs. Si MOSFET or IGBT, and also superior performance vs. SiC, below ~1200V ${\cdot}$ GaN E-HEMT is replacing Si MOSFET and IGBT in major application segments, and Industry Adoption will accelerate ${\cdot}$ Technology advances in GaN E-HEMT have made high-current true Normally-Off devices available in current ranges from 7A to 250A ${\cdot}$ While GaN has improved Properties vs. SiC or Si, different types of GaN devices offer different levels of performance or robustness ${\cdot}$ JEDEC Industrial-Grade Qualification of GaN E-HEMTs has been achieved, and Automotive Qualification is in progress.

  • PDF

Trends of Power Semiconductor Device (전력 반도체의 개발 동향)

  • Yun, Chong-Man
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2004.11a
    • /
    • pp.3-6
    • /
    • 2004
  • Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

  • PDF