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Current Spreading Layer와 에피 영역 도핑 농도에 따른 4H-SiC Vertical MOSFET 항복 전압 최적화

Optimization of 4H-SiC Vertical MOSFET by Current Spreading Layer and Doping Level of Epilayer

  • 안정준 (광운대학교 전자재료공학과) ;
  • 문경숙 (경원대학교 수학정보학과) ;
  • 구상모 (광운대학교 전자재료공학과)
  • Ahn, Jung-Joon (Department of Electronic Materials Engineering, Kwangwoon University) ;
  • Moon, Kyoung-Sook (Department of Mathematics and Information, Kyungwon University) ;
  • Koo, Sang-Mo (Department of Electronic Materials Engineering, Kwangwoon University)
  • 투고 : 2010.09.14
  • 심사 : 2010.09.20
  • 발행 : 2010.10.01

초록

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

키워드

참고문헌

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