• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.3
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• pp.205-210
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• 2000

Lead titanate thin films were fabricated on Si(100) wafer and ITO-coated glass substrates by metal organic chemical vapor deposition using ultrasonic spraying. When the ratio (Ti/Pb) of starting materials was 1.2, the films deposited on Si wafer had a single perovskite phase. The films deposited on ITO-coated glass had higher growth rate than that on Si wafer. As deposition temperature was increased from $530^{\circ}C$ to $570^{\circ}C$, dielectric constant was increased due to the increase of crystallinity and grain size. At $570^{\circ}C$, dielectric constant and dielectric loss of the films were 205 and 0.016, respectively. When the deposition temperature is higher than $600^{\circ}C$, dielectric constant was decreased.

• New & Renewable Energy
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• v.4 no.2
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• pp.68-73
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• 2008

It is very important that constitution of good hetero-junction interface with a high quality amorphous silicon thin films on very cleaned c-Si wafer for making high efficiency hetero-junction solar cells. For achieving the high efficiency solar cells, the inspection and management of c-Si wafer surface conditions are essential subjects. In this experiment, we analyzed the c-Si wafer surface very sensitively using Spectroscopic Ellipsometer for < ${\varepsilon}2$ > and u-PCD for effective carrier life time, so we accomplished < ${\varepsilon}2$ > value 43.02 at 4.25eV by optimizing the cleaning process which is representative of c-Si wafer surface conditions very well. We carried out that the deposition of high quality hydrogenated silicon amorphous thin films by RF-PECVD systems having high density and low crystallinity which are results of effective medium approximation modeling and fitting using spectroscopic ellipsometer. We reached the cell efficiency 12.67% and 14.30% on flat and textured CZ c-Si wafer each under AM1.5G irradiation, adopting the optimized cleaning and deposition conditions that we made. As a result, we confirmed that spectroscopic ellipsometry is very useful analyzing methode for hetero-junction solar cells which need to very thin and high quality multi layer structure.

• Journal of the Korean Ceramic Society
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• v.48 no.4
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• pp.312-315
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• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• Transactions on Electrical and Electronic Materials
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• v.15 no.4
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• pp.207-212
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• 2014

Aluminum-doped zinc oxide (AZO) films were deposited on SiOC/Si wafer by an RF-magnetron sputtering system, by varying the deposition parameters of radio frequency power from 50 to 200 W. To assess the correlation of the optical properties between the substrate and AZO thin film, photoluminescence was measured, and the origin of deep level emission of AZO thin films grown on SiOC/Si wafer was studied. AZO formed on SiOC/Si substrates exhibited ultraviolet emission due to exciton recombination, and the visible emission was associated with intrinsic and extrinsic defects. For the AZO thin film deposited on SiOC at low RF-power, the deep level emission near the UV region is attributed to an increase of the variations of defects related to the AZO and SiOC layers. The applied RF-power influenced an energy gap of localized trap state produced from the defects, and the gap increased at low RF power due to the formation of new defects across the AZO layer caused by lattice mismatch of the AZO and SiOC films. The optical properties of AZO films on amorphous SiOC compared with those of AZO film on Si were considerably improved by reducing the roughness of the surface with low surface ionization energy, and by solving the problem of structural mismatch with the AZO film and Si wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.953-957
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• 2002

Single crystal 3C-SiC (cubic silicon carbide) thin-films were deposited on Si(100) wafer up to the thickness of 4.3 ${\mu}{\textrm}{m}$ by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane; ｛CH$_{3}$｝$_{6}$ Si$_{2}$) at 135$0^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like crystal surface. The growth rate of the 3C-SiC film was 4.3 ${\mu}{\textrm}{m}$/hr. The 3C-SiC epitaxial film grown on Si(100) wafer was characterized by XRD (X-ray diffraction), AFM (atomic force microscopy), RHEED (reflection high energy electron diffraction), XPS (X-ray photoelecron spectroscopy), and Raman scattering, respectively. Two distinct phonon modes of TO (transverse optical) near 796 $cm^{-1}$ / and LO (longitudinal optical) near 974$\pm$1 $cm^{-1}$ / of 3C-SiC were observed by Raman scattering measurement. The heteroepitaxially grown film was identified as the single crystal 3C-SiC phase by XRD spectra (2$\theta$=41.5。).).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.700-704
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• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.1
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• pp.27-31
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• 2009

In this paper, the polymer adhesive bonding technology using wafer-level technology was investigated and warpage results were analyzed. Si and glass wafer was bonded after adhesive polymer layer and dam pattern for uniform state was patterned on glass wafer. In this study, warpage result decreased as the low of bonding temperature of Si wafer, bonding pressure and height of adhesive bonding layer. The availability of adhesive polymer bonding was confirmed by TC, HTC, Humidity soak test after dicing. The result is that defect has not found without reference to warpage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.301-307
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• 2002

Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.556-561
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• 2001

We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.