• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.660-666
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• 2010

30 nm thick Ni layers were deposited on a glass substrate by e-beam evaporation. Subsequently, 30 nm or 60 nm ${\alpha}-Si:H$ layers were grown at low temperatures ($<220^{\circ}C$) on the 30 nm Ni/Glass substrate by catalytic CVD (chemical vapor deposition). The sheet resistance, phase, microstructure, depth profile and surface roughness of the $\alpha-Si:H$ layers were examined using a four-point probe, HRXRD (high resolution Xray diffraction), Raman Spectroscopy, FE-SEM (field emission-scanning electron microscopy), TEM (transmission electron microscope) and AES depth profiler. The Ni layers reacted with Si to form NiSi layers with a low sheet resistance of $10{\Omega}/{\Box}$. The crystallinty of the $\alpha-Si:H$ layers on NiSi was up to 60% according to Raman spectroscopy. These results show that both nano-scale NiSi layers and crystalline Si layers can be formed simultaneously on a Ni deposited glass substrate using the proposed low temperature catalytic CVD process.

• Journal of Magnetics
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• v.12 no.1
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• pp.21-26
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• 2007

Si-based electromagnetic noise suppressors on coplanar waveguide transmission lines incorporated with a $SiO_2$ dielectric layer and a nanogranular Co-Fe-Al-O magnetic thin film are reported. Unlike glass-based devices, large signal attenuation is observed even in the bare structure without coating the magnetic thin film. Much larger signal attenuation is achieved in fully integrated devices. The transmission scattering parameter ($S_{21}$) is as small as -90 dB at 20 GHz at the following device dimensions; the thicknesses of the $SiO_2$ and Co-Fe-Al-O thin films are 0.1 $\mu$m and 1 $\mu$m, respectively, the length of the transmission line is 15 mm, and the width of the magnetic thin film is 2000 $\mu$m. In all cases, the reflection scattering parameter ($S_{11}$) is below -10 dB over the whole frequency band. Additional distributed capacitance formed by the Cu transmission line/$SiO_2$/Si substrate is responsible for these characteristics. It is considered that the present noise suppressors based on the Si substrate are a first important step to the realization of MMIC noise suppressors.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• Korean Journal of Materials Research
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• v.23 no.7
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• pp.379-384
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• 2013

In order to produce size-controllable Ag nanoparticles and a nanomesh-patterned Si substrate, we introduce a rapid thermal annealing(RTA) method and a metal assisted chemical etching(MCE) process. Ag nanoparticles were self-organized from a thin Ag film on a Si substrate through the RTA process. The mean diameter of the nanoparticles was modulated by changing the thickness of the Ag film. Furthermore, we controlled the surface energy of the Si substrate by changing the Ar or $H_2$ ambient gas during the RTA process, and the modified surface energy was evaluated through water contact angle test. A smaller mean diameter of Ag nanoparticles was obtained under $H_2$ gas at RTA, compared to that under Ar, from the same thickness of Ag thin film. This result was observed by SEM and summarized by statistical analysis. The mechanism of this result was determined by the surface energy change caused by the chemical reaction between the Si substrate and $H_2$. The change of the surface energy affected on uniformity in the MCE process using Ag nanoparticles as catalyst. The nanoparticles formed under ambient Ar, having high surface energy, randomly moved in the lateral direction on the substrate even though the etching solution consisting of 10 % HF and 0.12 % $H_2O_2$ was cooled down to $-20^{\circ}C$ to minimize thermal energy, which could act as the driving force of movement. On the other hand, the nanoparticles thermally treated under ambient $H_2$ had low surface energy as the surface of the Si substrate reacted with $H_2$. That's why the Ag nanoparticles could keep their pattern and vertically etch the Si substrate during MCE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.142-148
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• 1995

Sb ${\delta}$-doped Si layers were grown by Si MBE (Molecular Beam Epitaxy) system using substrate temperature modulation technique. The Si substrate temperatures were modulated between 350$^{\circ}C$ and 600$^{\circ}C$. The doping profile was as narrow as 41$\AA$ and the doping concentration of up to 3.5${\times}10^{20}cm^{3}$ was obtained. The film quality was as good as bulk material as verified by RHEED (Reflected High Energy Electron Diffraction), SRP (Spreading Resistance Profiling) and Hall measurement. Since the film quality is not degraded after the growth a Sb ${\delta}$-doped Si layer, the ${\delta}$-doped layers can be repeated as many times as we want. The doping technique is useful for many Si devices including small scale devices and those which utilize quantum mechanical effects.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.191-194
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• 1990

A $SnO_2$: F/$SiO_2$ duble layer on the sodalime glass is described for developing a low-cost substrate of a-Si solar cells. Dipping and Pyrosol method, have been used for thin film deposition, and electrical and optical properties have been analysed. Finally, p-i-n a-Si solar cells have been fabricated on this substrate by plasma CVD and their average efficiency is 4% approximately.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1998.09a
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• pp.91-95
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• 1998

Selectivity of SiC deposition on a Si substrate partially covered with a masking material was investigated by introducing HCl gas into hexamethyldisilane/H2 gas system during the deposition. the schedule of the precursor and HCl gas flows was modified so that the selectivity of SiC deposition between a Si substrate and a mask material should be improved. It was confirmed that the selectivity of SiC deposition was improved by introducing HCl gas. Also, the pulse gas flow technique was effective to enhance the selectivity.

• Journal of the Korean institute of surface engineering
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• v.48 no.3
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• pp.126-130
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• 2015

A high-pressure depletion method using plasma chemical vapor deposition (CVD) is often used to deposit hydrogenated microcrystalline silicon (${\mu}c-Si:H$) films of a low defect density at a high deposition rate. To understand proper deposition conditions of ${\mu}c-Si:H$ films for a high-pressure depletion method, Si films were deposited in a combinatorial way using a multi-hollow discharge plasma CVD method. In this paper the substrate temperature dependence of ${\mu}c-Si:H$ film properties are demonstrated. The higher substrate temperature brings about the higher deposition rate, and the process window of device quality ${\mu}c-Si:H$ films becomes wider until $200^{\circ}C$. This is attributed to competitive reactions between Si etching by H atoms and Si deposition.