• Journal of Advanced Navigation Technology
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• v.17 no.2
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• pp.196-201
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• 2013

In this paper, a dual-mode balanced filter with symmetric coupled composite right/left-handed transmission line is introduced. Unlike the other symmetric structure, this configuration has the ability to operate under both common- and differential-mode excitation. These properties are achievable through providing physical short circuit by means of ground vias at the center of each unit-cell along the symmetry plane of the structure. Because the CRLH unit-cells are operated under both common- and differential-mode excitation, we implemented a balanced filter using these properties. To validity these features, a five-cell four port coupled CRLH-TL is simulated, fabricated and measured and the obtained performances agree with the simulation results under both common- and differential-mode excitation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.40-44
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• 1997

Along with the rapid growth in microelectronics and power electronics technologies, various advanced control methods have been successfully implemented in real time and shown to be useful in controlling CO2 arc welding systems with high dynamic performance. In this paper, the slope of welding currents is controlled not to be so high in the case of short circuit welding mode. This results in less spatter. In addition, the data-base is constructed for the optimal welding conditions.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.359-362
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• 2016

In the PV (Photovoltaic) power system, a junction box collects the DC voltage generated from the PV module and transfers it to the PCS (power conditioning system). The junction box prevents damage caused by the voltage difference between the serially connected PV modules and provides convenience while repairing or inspecting the PV array. In addition, the junction box uses the diode to protect modules from the inverse current when the PV power system and electric power system are connected for use. However, by using the reverse blocking diode, heat is generated within the junction box while generating electric power, which decreases the generating efficiency, and causes short circuit and electric leakage. In this research, based on the purpose of improving the performance of the PV module by decreasing the heat generation within the junction box, a junction box with a built-in bypass circuit was designed/manufactured so that a certain capacity of current generated from the PV module does not run through the reverse blocking diode. The manufactured junction box was used to compare the electric power and heating power generated when the circuit was in the bypass/non-bypass modes. It was confirmed that the electric power loss and heat generation indicated a decrease when the circuit was in the bypass mode.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.2
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• pp.94-100
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• 2005

Korea Electrotechnology Research Institute(KERI) has successfully developed a 100hp-1800rpm-class high temperature superconducting(HTS) motor with high efficiency under partnership with Doosan Heavy Industries & Construction Co. Ltd. This motor has a HTS field winding and an air-cooled stator. The advantages of HTS motor can be represented by a reduction of 50% in both losses and size compared to conventional motors of the same rating. The cooling system is based on the heat transfer mechanism of the thermosyphon by using GM cryocooler as cooling source. The cold head is in contact with the condenser of a Ne-filled thermosyphon. Independently, the rotor assembly was tested at the stationary state and combined with stator. The HTS field winding could be cooled into below 30K. Test of open-circuit characteristics(OCC) and short-circuit characteristics(SCC) and load test with resistive load bank were conducted in generator mode. Also, load tests in motor mode driven by inverter were finished at KERI. Maximum operating current of field winding at 30K was 120A. From OCC and SCC test results synchronous inductance and synchronous reactance were 2.4mH, 0.49pu, respectively. Efficiency of this HTS machine was 93.3% in full load(100hp) test. This paper will present design, construction. and experimental test results of the 100hp HTS machine.

• Journal of Welding and Joining
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• v.13 no.4
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• pp.85-102
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• 1995

Weld quality of GMA welding processes is closely related to arc stability. Although many researches on arc stability have been performed, real-time estimation of arc stability has not been attempted. For instance, Mita proposed a off-line statistical method in which short circuiting and arcing time, and voltage and current wave forms were sampled to assess arc stability. But this method is not suitable to assess arc stability for GMA welder which employ inverter power source due to its controlled current and voltage wave forms. In this paper, the relationship between are stability and wire feed rate fluctuation is analyzed to propose new criterion for inverter power source. When arc voltage and arc current and arcing time are analyzed, we can assess arc stability only for short circuit transfer mode. When wire feed rate is analyzed, we can estimate arc stability udner the condition of spray transfer mode as well. Hence, the wire feed rate is chosen for monitoring process variable to cover possible metal transfer modes in GMAW. Through this research, it has been identified that arc stability in GMA welding processes is closely related to wire fed rate. When inverter power source is used, conventional statistical method of estimating arc stability, such as Mita index, is no longer valid due to its controlled voltage and current wave forms. Arc stability has been also examined in phase plane diagram.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.