• Journal of Distribution Science
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• v.15 no.1
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• pp.105-114
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• 2017

Purpose - Recently, domestic pharmaceutical market is growing steadily, but top-tier companies are concentrating on sales growth. In this market, SMEs, which account for more than 80% of the entire market, suffer from the problem of lower margins and increasing inventory costs. According to the government's policy changes related to pharmaceuticals, it is pointed out that the management of existing customers and the control of salespeople are important issues for pharmaceutical companies. This study investigates the effect of the control system on the salesperson in domestic pharmaceutical distribution channel on customer-oriented selling behaviors and sales performance. Research design, data, and methodology - To verify the proposed research model and test hypotheses, the authors selected 244 MR(medical representatives)'s responses which have currently relationship with doctors or pharmacists. This study carefully investigated the reliability, content validity, convergent validity, and discriminant validity of the proposed model. Results - The authors find out the following results: capacity control, activity control, and self control have positive effects on customer-oriented selling behaviors and customer-oriented selling behaviors have a positive effect on sales performance. In addition, we present alternative model to check the direct effect between the control systems and the sales performance, but control system factors except self control have no direct influence. Conclusions - First of all, competency control and activity control increases the customer-oriented selling behavior of the salesperson. This means that the salesperson's sales skill, negotiation skill, customer access skill, presentation ability, monitoring, direction and evaluation are important and it is also important to control activities to check the number of visits to customers, report preparation, and customer service etiquette. Second, the fact that self-control of salesperson affects the customer-oriented selling behavior suggests that self-control is not controlled by external factors but rather establishes short/long-term goals. Therefore, it is important for sales organization to create an environment in which members can induce persistent incentives for self-control. Finally, output control did not affect customer-oriented sales behavior, which is less likely to form confidence or motivation to MRs when output control is perceived as a means of monitoring, supervising, or controlling rather than providing information to salespeople.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.615-624
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• 2014

In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger band-structure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMG-CNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS'10 requirements better than CNTs.

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.84-84
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• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Journal of information and communication convergence engineering
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• v.21 no.2
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• pp.103-109
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• 2023

We investigated the antipodal-symmetric dispersion maps of a dispersion-managed link with a midway optical phase conjugator to compensate for the distorted 960 Gb/s wavelength division multiplexed (WDM) signal caused by these effects. The proposed antipodal-symmetric dispersion map has various shapes depending on the detailed design scheme. We confirmed that the dispersion-managed link designed with the dispersion map of the antipodal-symmetric structure is more advantageous than the conventional uniform dispersion map for compensating WDM channels. It was also confirmed that among the antipodal-symmetric structures, the dispersion map configured with the S-1-profile, in which S is inverted up and down, was more effective for distortion compensation than the dispersion map configured with the S-profile. In particular, we confirmed that the S-1-profile can broaden the optical pulse width intensively at a short transmission distance, more effectively compensating for the distorted WDM channel. Because this structure makes the intensity of the optical pulse relatively weak, it can decrease the nonlinear Kerr effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.100-104
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• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.803-812
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• 2006

This paper analytically evaluates the FEC(Forward Error Correction) symbol size's effect on the performance and energy consumption of 802.11 protocol with the block FEC algorithm over WSN(Wireless Sensor Network). Since the basic recovery unit of block FEC algorithms is symbols not bits, the FEC symbol size affects the packet correction rate even with the same amount of FEC check bits over a given WSN channel. Precisely, when the same amount of FEC check bits are allocated, the small-size symbols are effective over channels with frequent short bursts of propagation errors while the large ones are good at remedying the long rare bursts. To estimate the effect of the FEC symbol site, the paper at first models the WSN channel with Gilbert model based on real packet traces collected over TIP50CM sensor nodes and measures the energy consumed for encoding and decoding the RS (Reed-Solomon) code with various symbol sizes. Based on the WSN channel model and each RS code's energy expenditure, it analytically calculates the transmission efficiency and power consumption of 802.11 equipped with RS code. The computational analysis combined with real experimental data shows that the RS symbol size makes a difference of up to 4.2% in the transmission efficiency and 35% in energy consumption even with the same amount of FEC check bits.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.294.1-294.1
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• 2016

Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.