• Title/Summary/Keyword: Short channel

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Improved Performance and Suppressed Short-Channel Effects of Polycrystalline Silicon Thin Film Transistors with Electron Cyclotron Resonance $N_2$O-Plasma Gate Oxide (Electron Cyclotron Resonance $N_2$O-플라즈마 게이트 산화막을 사용한 다결정 실리콘 박막 트랜지스터의 성능 향상 및 단채널 효과 억제)

  • 이진우;이내인;한철희
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.12
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    • pp.68-74
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    • 1998
  • Improved performance and suppressed short-channel effects of polysilicon thin film transistors (poly-Si TFTs) with very thin electron cyclotron resonance (ECR) $N_2$O-plasma gate oxide have been investigated. Poly-Si TFTs with ECR $N_2$O-plasma oxide ($N_2$O-TFTs) show better performance as well as suppressed short-channel effects than those with conventional thermal oxide. The fabricated $N_2$O-TFTs do not show threshold voltage reduction until the gate length is reduced to 3 ${\mu}{\textrm}{m}$ for n-channel and 1 ${\mu}{\textrm}{m}$ for p-channel, respectively. The improvements are due to the smooth interface, passivation effects, and strong Si ≡ N bonds.

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TRPC-Mediated Current Is Not Involved in Endocannabinoid-Induced Short-Term Depression in Cerebellum

  • Chang, Won-Seok;Kim, Jun;Kim, Sang-Jeong
    • The Korean Journal of Physiology and Pharmacology
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    • v.16 no.2
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    • pp.139-144
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    • 2012
  • It has been reported that activation of metabotropic glutamate receptor 1 (mGluR1) can mediate endocannabinoid-induced short-term depression of synaptic transmission in cerebellar parallel fiber (PF)-Purkinje cell (PC) synapse. mGluR1 has signaling pathways involved in intracellular calcium increase which may contribute to endocannabinoid release. Two major mGluR1-evoked calcium signaling pathways are known: (1) slow-kinetic inward current carried by transient receptor potential canonical (TRPC) channel which is permeable to $Ca^{2+}$; (2) $IP_3$-induced calcium release from intracellular calcium store. However, it is unclear how much each calcium source contributes to endocannabinoid signaling. Here, we investigated whether calcium influx through mGluR1-evoked TRPC channel contributes to endocannabinoid signaling in cerebellar Purkinje cells. At first, we applied SKF96365 to inhibit TRPC, which blocked endocannabinoid-induced short-term depression completely. However, an alternative TRP channel inhibitor, BTP2 did not affect endocannabinoid-induced short-term depression although it blocked mGluR1-evoked TRPC currents. Endocannabinoid signaling occurred normally even though the TRPC current was mostly blocked by BTP2. Our data imply that TRPC current does not play an important role in endocannabinoid signaling. We also suggest precaution in applying SKF96365 to inhibit TRP channels and propose BTP2 as an alternative TRPC inhibitor.

Analysis of Threshold Voltage Roll-off for Ratio of Channel Length and Thickness in DGMOSFET (DGMOSFET에서 채널길이와 두께 비에 따른 문턱전압변화분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.10
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    • pp.2305-2309
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    • 2010
  • In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off and drain induced barrier lowing have been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

Analysis of Threshold Voltage Roll-off for Ratio of Channel Length and Thickness in DGMOSFET (DGMOSFET에서 채널길이와 두께 비에 따른 문턱전압변화분석)

  • Jung, Hak-Kee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.765-767
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    • 2010
  • In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off has been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

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Multi-channel Long Short-Term Memory with Domain Knowledge for Context Awareness and User Intention

  • Cho, Dan-Bi;Lee, Hyun-Young;Kang, Seung-Shik
    • Journal of Information Processing Systems
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    • v.17 no.5
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    • pp.867-878
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    • 2021
  • In context awareness and user intention tasks, dataset construction is expensive because specific domain data are required. Although pretraining with a large corpus can effectively resolve the issue of lack of data, it ignores domain knowledge. Herein, we concentrate on data domain knowledge while addressing data scarcity and accordingly propose a multi-channel long short-term memory (LSTM). Because multi-channel LSTM integrates pretrained vectors such as task and general knowledge, it effectively prevents catastrophic forgetting between vectors of task and general knowledge to represent the context as a set of features. To evaluate the proposed model with reference to the baseline model, which is a single-channel LSTM, we performed two tasks: voice phishing with context awareness and movie review sentiment classification. The results verified that multi-channel LSTM outperforms single-channel LSTM in both tasks. We further experimented on different multi-channel LSTMs depending on the domain and data size of general knowledge in the model and confirmed that the effect of multi-channel LSTM integrating the two types of knowledge from downstream task data and raw data to overcome the lack of data.

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

  • Sahu, P.K.;Mohapatra, S.K.;Pradhan, K.P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.647-654
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    • 2013
  • The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters

  • Yu, Sang-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.75-87
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    • 2012
  • A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.

A Study on the Threshold voltage and I-V Characteristics in the Ion-implanted Short channel E-IGFET(II) (Ion-Implanted short Channel E-IGFET의 Threshold 전압과 I-V특성에 관한 연구(II))

  • Son, Sang-Hui;Kim, Hong-Bae;Gwak, Gye-Dal
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.22 no.4
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    • pp.51-58
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    • 1985
  • A simple model for the impurity profile in an ion-implanted channel layer of an enhance-ment type IGFET is assumed and a simple expression for the threshold voltage is derived by the assumed impurity profile. In application, the concept of correction factor K is used and the value of threshold voltage is well agreed with experimental value. Also, 1-V character-istics curve is well agreed with experimental value. In addition, this program is packaged and is utilized.

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Fabrication and characteristics of short channel nonvolatile SNOSFET memory devices (Short channel 비휘발성 SNOSFET 기억소자의 제작과 특성)

  • 강창수
    • Electrical & Electronic Materials
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    • v.4 no.3
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    • pp.259-266
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    • 1991
  • 1.5.mu.m의 찬넬길이를 갖는 short channel 비휘발성 SNOSFET 기억소자를 기존의 CMOS 1 Mbit 공정기술을 이용하여 제작하고 I$_{d}$-V$_{d}$ 및 I$_{d}$- V$_{g}$특성과 스윗칭 및 기억유지특성을 조사하였다. 그 결과 제작한 소자는 논리회로 설계에 적절한 전도특성을 가졌으며 스윗칭시간은 인가전압의 크기에 의존함을 보였다. 그리고 3V의 memory window 크기를 얻기 위해서 V$_{w}$ =+34V, t$_{w}$ =50.mu.sec 및 V$_{e}$=-34V, t$_{e}$=500.mu.sec의 펄스전압으로 각각 write-in과 erase할 수 있었다. 또한 기억상태는 10년이상 유지할 수 있음을 알 수 있었다.

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Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

  • Suh, Chung-Ha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.2
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    • pp.111-120
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    • 2011
  • A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.