• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Review of KIISC
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• v.16 no.4
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• pp.25-33
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• 2006

중국의 Wang 교수 등은 2004년부터 차분 공격을 이용하여 대표적인 해쉬함수인 MD4, MD5, RIPEMD, HAVAL, SHA-0에 대한 충돌쌍을 찾았다. 그들은 아직까지 SHA-1에 대한 충돌쌍을 찾지는 못했지만 생일 공격보다 빠른 방법으로 SHA-1의 충돌쌍을 찾을 수 있음을 이론적으로 보였으며 58단계 SHA-1(SHA-1의 전체는 80단계)에 대해서는 구체적인 충돌쌍을 찾았다. 본 논문에서는 Wang 교수 등이 개발한 차분 공격법에 대해서 살펴보기로 한다.

• Journal of Microbiology and Biotechnology
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• v.21 no.9
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• pp.979-987
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• 2011

Culture pH change has some important roles in signal transduction and secondary metabolism. We have already reported that acidic pH shock enhanced actinorhodin production in Streptomyces coelicolor. Among many potential governing factors on pH variation, the putative $Na^+/H^+$ antiporter (sha) genes in S. coelicolor have been investigated in this study to elucidate the association of the sha on pH variation and secondary metabolism. Through the transcriptional analysis and overexpression experiments on 8 sha genes, we observed that most of the sha expressions were promoted by pH shock, and in the opposite way the pH changes and actinorhodin production were enhanced by the overexpression of each sha. We also confirmed that sha8 especially has a main role in maintaining cell viability and pH homeostasis through $Na^+$ extrusion, in salt effect experiment under the alkaline medium condition by deleting sha8. Moreover, this gene was observed to have a function of pH recovery after pH variation such as the pH shock, being able to cause the sporulation. However, actinorhodin production was not induced by the only pH recovery. The sha8 gene could confer on the host cell the ability to recover pH to the neutral level after pH variation like a pH drop. Sporulation was closely associated with this pH recovery caused by the action of sha8, whereas actinorhodin production was not due to such pH variation patterns alone.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Journal of Microbiology and Biotechnology
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• v.23 no.2
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• pp.149-155
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• 2013

Heterologous expression of a putative $K^+/H^+$ antiporter of Streptomyces coelicolor A3(2) (designated as sha4) in E. coli and Streptomyces hygroscopicus JCM4427 showed enhanced tolerance to $K^+$ stress, acidic-pH shock, and/or geldanamycin production under $K^+$ stress. In a series of $K^+$ extrusion experiments with sha4-carrying E. coli deficient in the $K^+/H^+$ antiporter, a restoration of impaired $K^+$ extrusion activity was observed. Based on this, it was concluded that sha4 was a true $K^+/H^+$ antiporter. In different sets of experiments, the sha4-carrying E. coli showed significantly improved tolerances to $K^+$ stresses and acidic-pH shock, whereas sha4-carrying S. hygroscopicus showed an improvement in $K^+$ stress tolerance only. The sha4-carrying S. hygroscopicus showed much higher geldanamycin productivity than the control under $K^+$ stress condition. In another set of experiments with a production medium, the secretion of geldanamycin was also significantly enhanced by the expression of sha4.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.295-301
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• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.