Fig. 1. 3-D array representation of state. 그림 1. 3차원 배열로 표현된 state
Fig. 2. Sponge construction of SHA-3. 그림 2. SHA-3의 스폰지 구조
Fig. 3. Architectures of SHA-3 hash processor depending on datapath bit-width. 그림 3. 데이터패스 크기에 따른 SHA-3 해시 프로세서의 구조
Fig. 4. Performance analysis results for determining SHA-3 hash processor architecture. 그림 4. SHA-3 해시 프로세서의 아키텍처 결정을 위한 성능분석 결과
Fig. 5. Architecture of SHA-3 processor. 그림 5. SHA-3 프로세서의 구조
Fig. 6. FSM of Padder block. 그림 6. Padder 블록의 유한상태머신
Fig. 7. Round block. 그림 7. 라운드 블록
Fig. 8. KECCAK-p permutation block. 그림 8. KECCAK-p 순열 변환 블록
Fig. 9. Timing diagram of SHA-3 hash processor. 그림 9. SHA-3 해시 프로세서의 타이밍 도
Fig. 10. Cortex-M0 interface of SHA-3 slave. 그림 10. SHA-3 슬레이브의 Cortex-M0 인터페이스
Fig. 11. HW/SW co-verification of SHA-3 processor and Cortex-M0 with FPGA implementation. 그림 11. FPGA 구현에 의한 SHA-3 프로세서와 Cortex-M0의 하드웨어/소프트웨어 통합 검증
Table. 1. Comparison of SHA-3 hash processors. 표 1. SHA-3 해시 프로세서 비교
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