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http://dx.doi.org/10.6109/jkiice.2018.22.1.109

An Area-efficient Design of SHA-256 Hash Processor for IoT Security  

Lee, Sang-Hyun (School of Electronic Engineering, Kumoh National Institute of Technology)
Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.22, no.1, 2018 , pp. 109-116 More about this Journal
Abstract
This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.
Keywords
Secure Hash Algorithm (SHA); SHA-256; hash processor; message digest; information security; IoT security;
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Times Cited By KSCI : 1  (Citation Analysis)
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