• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.665-668
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• 2003

In this paper, we have designed and implemented the RAID controller board which connects to the host computer with serial ATA interface and connects to the disks with parallel ATA interface. Serial ATA interface is proposed to overcome the design limitation of parallel ATA while enabling the storage interface to scale with the slowing media rate demands for PC platforms. Serial ATA is to replace parallel ATA with the compatibility with existing operating systems and drivers, adding performance headroom for years to come. It Moreover, serial ATA provides even faster transfer rate of 150 Mbytes/s which is larger than that of current parallel ATA. The RAID controller board designed in this paper combines up to 4 disks with parallel ATA interface, and connects to PC host computer with serial ATA interface. We have implemented RAID controller using Verilog HDL language with FPGA chip. The RAID controller supports RAID level 0 and 1 functionality. Experimently, the average read/write performance of parallel ATA interface is about 30 Mbytes/s. Therefore, when 4 parallel disks is connected to the RAID controller board, we can get almost full throughput of serial ATA protocol using the RAID level 0 configuration with 4 disks.

• Journal of Advanced Navigation Technology
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• v.12 no.5
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• pp.464-469
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• 2008

The RS-232C (Unbalanced serial) and RS-485 (balanced serial) are standard in serial communication. RS-485 uses a differential electrical signal, as opposed to unbalanced signals referenced to ground with the RS-232. Differential transmission, which uses two lines each for transmit and receive signal results in greater noise immunity and longer distances as compared to the RS-232C. The greater noise immunity and distance are big advantages in industrial environments. In general, one protocol on one serial interface is very normal application. In this study, we implemented multi protocols on one serial RS-485 interface and examine the performance and result with hanging multi equipments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.522-525
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• 2006

Recently, mobile devices support multi-functions such as 3D game, wireless internet, moving pictures, DMB, GPS, and PMP. Bigger size of display device is indispensable to support these functions and higher speed of the interface is needed. However, conventional parallel interfaces between processor and display nodule are not competent enough for that high speed transfers. High-speed serial interface is beginning to appear as an alternative for parallel interface. The advantages of the serial interface are high bandwidth, small number of interconnections, low-power consumption, and good quality of electro-magnetic interference. In this paper, we implement serial interface and use it for a display module. LVDS is used for PHY layer and a defined packet is used for link layer. The feature of the implemented serial interface is the reduced number of interconnections with enough bandwidth.

• ETRI Journal
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• v.24 no.6
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• pp.462-464
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• 2002

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.195-197
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• 2006

In this paper, an interface unit is designed to efficiently monitor transmission data in Controller Area Network(CAN)-based control systems. The CAN uses a serial multi master communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1Mbps. The interface unit is composed of a DSP controller which collects data on the CAN bus and transfers data to a personal computer via serial communication to save and display of interesting signals. The experimental system consists of three DSP controllers which represent electronic control units of a vehicle, an interface unit for analysing the data on the bus, and a graphic monitoring program coded on the Windows platform. The validity and the effectiveness of the proposed simple type of CAN interface unit are shown through the experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1084-1096
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• 2016

This paper presents method of design and analysis of a high-speed serial interface connector with a data rate of 12.5 Gbps. A high-speed serial interface connector is composed of various material and complex structures. It is very difficult to match the impedance of each discontinuous portion of connector. Therefore, this paper proposes the structure of a connector line that be simplified a connector. In the structure of proposed connector line, this research presents a method for extracting R, L, C and G parameters, analyzing the differential mode impedance, and minimizing the impedance discontinuity using time domain transmissometry and time domain reflectometry. This paper applies the proposed methods in the connector line to the high-speed serial interface connector. The proposed high-speed serial interface connector, which consists of forty-four pins, is analyzed signal transmission characteristics by changing the width and spacing of the four pins. According to the analysis result, as the width of the ground pin increases, the impedance decreases slightly. And as the distance between the ground pin and the signal pin increases, the impedance increases. In addition, as the width of the signal pin increases, the impedance decreases. And as the distance between the signal pin and the signal pin increases, the impedance decreases. The impedance characteristic of initial connector presents ranges from 96 to $139{\Omega}$. Impedance characteristic after applying the structure of proposed connector is shown as a value between 92.6 to $107.5{\Omega}$. This value satisfies the design objective $100{\Omega}{\pm}10%$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.35-40
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• 2023

In this paper, a serial wireless LAN virtual communication module that allows microprocessors to communicate wirelessly with other peripheral devices is developed as part of a study to build an online virtual experiment system that allows them to practice virtually anytime, anywhere in microprocessor application education in electrical and electronic control engineering. The developed module is connected to the microprocessor in the virtual experiment system through serial interface. The serial data is sent to and received from peripheral devices through the wireless LAN interface of the host computer where the virtual experiment software is being performed. In order to verify the function of the developed serial wireless LAN virtual communication module, experiments were conducted in which a microprocessor in the virtual experiment system exchanged data with an Android smartphone through a wireless LAN interface of a host computer. The developed serial wireless LAN communication module is expected to enable virtual microprocessors to communicate with surrounding real devices through wireless LAN, which can be efficiently used in microprocessor application education.