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http://dx.doi.org/10.5573/ieie.2014.51.12.046

Performance Analysis of High-Speed Transmission Line for Terabit Per Second Switch Fabric Interface  

Choi, Chang-Ho (Electronics and Telecommunication Research Institute)
Kim, Whan-Woo (Department of Electronic Engineering, Chungnam National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.12, 2014 , pp. 46-55 More about this Journal
Abstract
PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.
Keywords
High-speed transmission line; Via stub; Crosstalk; PCB; S-parameter;
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