• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.665-668
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• 2003

In this paper, we have designed and implemented the RAID controller board which connects to the host computer with serial ATA interface and connects to the disks with parallel ATA interface. Serial ATA interface is proposed to overcome the design limitation of parallel ATA while enabling the storage interface to scale with the slowing media rate demands for PC platforms. Serial ATA is to replace parallel ATA with the compatibility with existing operating systems and drivers, adding performance headroom for years to come. It Moreover, serial ATA provides even faster transfer rate of 150 Mbytes/s which is larger than that of current parallel ATA. The RAID controller board designed in this paper combines up to 4 disks with parallel ATA interface, and connects to PC host computer with serial ATA interface. We have implemented RAID controller using Verilog HDL language with FPGA chip. The RAID controller supports RAID level 0 and 1 functionality. Experimently, the average read/write performance of parallel ATA interface is about 30 Mbytes/s. Therefore, when 4 parallel disks is connected to the RAID controller board, we can get almost full throughput of serial ATA protocol using the RAID level 0 configuration with 4 disks.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.365-368
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• 2003

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.39-45
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• 2004

This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of IKEEE
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• v.15 no.2
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.127-129
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• 2003

현재 데이터의 양은 인터넷 관련 비즈니스/전자상거래 등 인터넷 프로토콜(IP) 네트워크를 이용한 저장 장치의 데이터 증가를 가져오게 되었다. 본 논문에서는 펜티엄 프로세서, 고속 이더넷 IDE RAID 시스템 (IDE RAID Controller와 IDE 디스크로 구성)과 iSCSI(Internet Small Computer System Interface) 프로토콜을 이용하여 저렴한 비용으로 비교적 우수한 성능의 리눅스 기반의 저장장치 시스템을 설계 구현하였다. 또한 저장장치 시스템의 벤치마크 프로그램인 ioZone을 사용하여 SCSI RAID 시스템으로 구성된 저장 장치 시스템과의 성능을 비교 분석하여 가격대비 성능이 비교적 우수함을 보여준다. 끝으로. 향후 SATA(Serial ATA)를 이용한 저장장치 시스템의 전망을 가늠해본다.

• KIISE Transactions on Computing Practices
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• v.23 no.7
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• pp.428-433
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• 2017

Recently, the demand for high performance non-volatile memory storage devices that can replace existing hard disks has been increasing in environments requiring high performance computing such as data-centers and social network services. The performance of such non-volatile memory can greatly depend on the interface between the host and the storage device. With the evolution of storage interfaces, the non-volatile memory express (NVMe) interface has emerged, which can replace serial attached SCSI and serial ATA (SAS/SATA) interfaces based on existing hard disks. The NVMe interface has a higher level of scalability and provides lower latency than traditional interfaces. In this paper, an evaluation and analysis are conducted of the performance of NVMe storage devices through various workloads. We also compare and evaluate the cost efficiency of NVMe SSD and SATA SSD.

• Journal of the Institute of Convergence Signal Processing
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• v.18 no.2
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• pp.55-61
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• 2017

In radio astronomy, high-capacity HDDs are being used to save huge amounts of HDDs in order to record the observational data. For VLBI observations, observational speeds increase and huge amounts of observational data must be stored as they expand to broadband. As the HDD is frequently used, the number of failures occurred, and then it takes a lot of time to recover it. In addition, if a failed HDD is continuously used, observational data loss occurs. And it costs a lot of money to buy a new HDD. In this study, we developed the integrity verification system of the Serial ATA HDD using FirmOS. The FirmOS is an OS that has been developed to function exclusively for specific purposes on a system having a general server board and CPU. The developed system performs the process of writing and reading specific patterns of data in a physical area of the SATA HDD based on a FirmOS. In addition, we introduced a method to investigate the integrity of HDD integrity by comparing it with the stored pattern data from the HDD controller. Using the developed system, it was easy to determine whether the disk pack used in VLBI observations has error or not, and it is very useful to improve the observation efficiency. This paper introduces the detail for the design, configuration, testing, etc. of the SATA HDD integrity verification system developed.