• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.251-263
• /
• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.15-24
• /
• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.136-141
• /
• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Journal of Digital Contents Society
• /
• v.18 no.6
• /
• pp.1193-1198
• /
• 2017

The IGBT structure developed in this paper is used as a high power switch semiconductor for DC transmission and distribution and it is expected that it will be used as an important electronic device for new and long distance DC transmission in the future by securing fast switching speed and improved breakdown voltage characteristic. As a new type of next generation power semiconductors, it is designed to improve the switching speed while at the same time improving the breakdown voltage characteristics, reducing power loss characteristics, and achieving high current density advantages at the same time. These improved properties were obtained by further introducing SiO2 into the N-drift region of the Planar IGBT and were compared and analyzed using the Sentaurus TCAD simulation tool.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.756-761
• /
• 2019

In this paper, we propose SC-SJ(Shielding Connected-Super Junction) UMOSFET structure in which p-pillars of conventional 4H-SiC Super Junction UMOSFET structures are placed under the shielding region of UMOSFET. In the case of the proposed SC-SJ UMOSFET, the p-pillar and the shielding region are coexisted so that no breakdown by the electric field occurs in the oxide film, which enables the doping concentration of the pillar to be increased. As a result, the on-resistance is lowered to improve the static characteristics of the device. Through the Sentaurus TCAD simulation, the static characteristics of proposed structure and conventional structure were compared and analyzed. The SC-SJ UMOSFET achieves a 50% reduction in on-resistance compared to the conventional structure without any change in the breakdown voltage.

• Journal of IKEEE
• /
• v.25 no.2
• /
• pp.371-375
• /
• 2021

In this paper, a SiC-based LIGBT structure that can be used at high voltage and high temperature is presented. In order to improve the low current characteristic, a dual-emitter symmetrical around the gate is inserted. In order to verify the characteristics of the proposed device, simulation and design were conducted using Sentaurus TCAD simulation, and a comparative study was conducted with a general LIGBT. In addition, splitting was performed by designating a variable for the length of the N-drift region in order to verify the electrical characteristics of the minority carriers. As a result of the simulation it was confirmed that the proposed dual-emitter structure flows a higher current at the same voltage than the conventional LIGBT.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.449.2-449.2
• /
• 2014

태양전지용 III-V족 화합물 반도체 물질인 GaAs는 1.42eV의 Energy Band-gap (Eg)을 가지고 있기 때문에 이론적으로 단일접합 태양전지로는 가장 높은 수준의 광-전 변환효율 달성이 가능하다. 비록 emitter의 조건 가변으로 설정을 했음에도 불구하고, 처음 기본적인 구조였던 emiier 두께 75 nm, 도핑농도 상에서 효율이 24.53%가 될 정도로 큰 효율이 나오게 되었다. TCAD simulation을 이용하여 emitter의 도핑농도와 두께를 가변하여 가장 높은 효율이 나오는 emitter 조건을 찾는 실험을 진행하였다. 시뮬레이션 결과 emitter두께 100 nm에서 도핑농도가 인 경우에 Voc=28.43, Jsc=25.84, Jph=29.12, FF=87.76%, 효율은 25.84%가 나오는 것을 확인 수 있었다.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.592-597
• /
• 2020

Since SiC has 10 times higher breakdown field and 3 times higher energy gap than Si, it is possible to manufacture an excellent power MOSFET with a high breakdown voltage. However, since it has a high on-resistance due to low mobility, a Trench MOSFET has been proposed to lower it, but at the same time, it has a problem that BV decreases. The purpose of this paper is to design a 1200V trench MOSFET, and to solve this, split Epi depth, Trench depth, and Trench depth to Epi depth, which are important variables for BV and Ron, to achieve maximum electric field, BV, Ron's reliability characteristics were compared and analyzed. As the epi depth increased, the trench depth decreased, and the epi depth decreased at the trench depth, the maximum electric field decrease, BV increase, and Ron increase were confirmed. All results were simulated by sentaurus TCAD.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.94-100
• /
• 2015

In this paper, 50V power U-MOSFET which replace the body(PN) diode with Schottky is proposed. As already known, Schottky diode has the advantage of reduced reverse recovery loss than PN diode. Thus, the power MOSFET with integrated Schottky integrated can minimize the reverse recovery loss. The proposed Schottky body diode U-MOSFET(SU-MOS) shows reduction of reverse recovery loss with the same transfer, output characteristic and breakdown voltage. As a result, 21.09% reduction in peak reverse current, 7.68% reduction in reverse recovery time and 35% improvement in figure of merit(FOM) are observed when the Schottky width is $0.2{\mu}m$ and the Schottky barrier height is 0.8eV compared to conventional U-MOSFET(CU-MOS). The device characteristics are analyzed through the Synopsys Sentaurus TCAD tool.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.284-292
• /
• 2020

SiC-based devices perform well in high-voltage environments of more than 1200V compared to silicon devices, and are particularly stable at very high temperatures. Therefore, 1700V UMOSFET has been actively researched and developed for the use of electric power systems such as electric vehicles and aircrafts. In this paper, we analysed thermal variations of critical variables (breakdown voltage (BV), on-resistance (R_on), threshold voltage (v_th), and transconductance (g_m)) for the three type 1700V UMOSFETs-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), and Local Floating Superjunction UMOSFET (LFS-UMOSFET). All three devices showed BV increase, R_on increase, v_th decrease, and g_m decrease with increasing temperature. However, there are differences in BV, R_on, v_th, g_m according to the structural differences of the three devices, and the degree and cause of the analysis were compared. All results were simulated using sentaurus TCAD.