• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.72-77
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• 2016

As the semiconductor production technology has gradually developed and intra-market competition has grown fiercer, the caliber of Si Wafer for semiconductor production has increased as well. And semiconductors have become integrated with higher density. Presently the Si Wafer caliber has reached up to 450 mm and relevant production technology has been advanced together. Electrostatic chuck is an important device utilized not only for the Wafer transport and fixation but also for the heat treatment process based on plasma. To effectively control the high calories generated by plasma, it employs a refrigerant-based cooling method. Amid the enlarging Si Wafers and semiconductor device integration, effective temperature control is essential. Therefore, uniformed temperature distribution in the electrostatic chuck is a key factor determining its performance. In this study, the form of refrigerant flow channel will be investigated for uniformed temperature distribution in electrostatic chuck.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.142-147
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• 2022

After introducing Hybrid Bonding technology into image sensors using stacked sensors and image processors, large quantity production became possible. As a result, it is currently used in most of the CMOS image market in smartphones and other image-based devices worldwide, and almost all stacked CIS manufacturing sites have focused on miniaturization using hybrid bonding. In this study, an upper wafer handling module for Wafer to Wafer Hybrid Bonding developed to increase the alignment and precision between wafers when wafer bonding. The module was divided two parts to reduce error of both the alignment and degree of precision during wafer bonding. Wafer handling module developed both new Tip/Tilt system controlling θx,θy of upper wafer and striker to push upper wafer. Based on this, it was confirmed through the stability evaluation that the upper wafer handling module can be controlled without any problem during W2W hybrid bonding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.120-124
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• 2004

본 연구는 Diluted Ceria 입자를 사용한 $SiO_2$(Oxide) CMP 현상에 대한 내용이다. Ceria Slurry의 경우 Silica Slurry와 비교하였을 때 Oxide Wafer 표면과 축합 화학반응을 일으키며 Chemistry Dominant한 CMP Mechanism을 따르고, Wafer Center Removal Rate(RR) Fast 의 특성을 가진다. Ceria Slurry의 문제점인 연마 불균일도를 해결하기 위해 Tribological System을 이용하였다. CMP Tribology는 Pad-Slurry 유막-Wafer의 System을 가지며 윤활막에 작용하는 마찰계수(COF)가 주요 인자이다. Tribology에 적용되는 Stribeck Curve를 통해 Slurry 윤활막의 두께(h) 정도를 예상할 수 있으며, 이 윤활막의 두께를 조절함으로써 Uniformity 향상이 가능하다. 이 Ceria Slurry CMP의 연마 불균일도를 향상시킬 수 있는 방법으로 pH 조절 및 점도 증가가 있다. Ceria 입자 CMP는 분산액의 pH 변화에 강한 작용을 받게 되며 PH5 근방에서 최적화된 Uniformity가 가능하다. 점도를 증가시키는 경우 유막 h가 증가하게 되어 Ceria Slurry의 유동이 균일 분포 상태에 가까워지며 Wafer Uniformity 향상이 가능하다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.17-23
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• 2023

In semiconductor manufacturing processes, a cleaning process is important that can remove sub-micron particles. Conventional wet cleaning methods using chemical have limits in removing nano-particles. Thus, physical forces of a mechanical vibration up to 1 MHz frequency, was tried to aid in detaching them from the substrates. In this article, we developed a 1 MHz quartz megasonic for a bare wafer cleaning using finite element analysis. At first, a 1 MHz megasonic prototype was manufactured. Using the results, a main product which can improve a particle removal performance, was analyzed and designed. The maximum impedance frequency was 992 kHz, which agreed well with the experimental value of 986 kHz (0.6% error). Acoustic pressure distributions were measured, and the result showed that maximum / average was 400.0~432.4%, and standard deviation / average was 46.4~47.3%. Finally, submicron particles were deposited and cleaned for the assessment of the system performance. As a result, the particle removal efficiency (PRE) was proved to be 92% with 11 W power. Reflecting these results, the developed product might be used in the semiconductor cleaning process.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.31-35
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• 2009

In the silicon wafer polishing process, the mounting stage of silicon wafer on the ceramic carrier block has been using the polishing template which utilizes the porous surface instead of traditional wax mounting method. Here in this article, the experimental study is carried out in order to study the wafer demounting by water jet and the effects of operating conditions such as the water jet flowrate and the number of water jet nozzles on the wafer demounting time. It is found that the measured wafer demounting time is inversely proportional to the water flowrate per nozzle, regardless of number of nozzles used; implying that the stagnation pressure by the water jet impingement is the dominant key factor. Additionally, by using the transparent disk instead of wafer, the air bubble formation and growth is observed under the disk, making the passage of water flow, and subsequently demounting the wafer from the porous pad.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Journal of Korean Institute of Industrial Engineers
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• v.35 no.4
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• pp.266-279
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• 2009

This paper focuses on the problem of scheduling wafer lots with limited waiting times between pairs of consecutive operations in a semiconductor wafer fabrication facility. For the problem of minimizing total tardiness of orders, we develop a priority rule based scheduling method in which a scheduling decision for an operation is made based on the states of workstations for the operation and its successor or predecessor operation. To evaluate performance of the suggested scheduling method, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation experiments show that the suggested method performs better than a method suggested in other research and the one that has been used in practice.