• 설비공학논문집
• /
• 제5권2호
• /
• pp.130-140
• /
• 1993

Average particle deposition velocity toward a horizontal semiconductor wafer in vertical airflow is measured by a wafer surface scanner(PMS SAS-3600). Use of wafer surface scanner requires very short exposure time normally ranging from 10 to 30 minutes, and hence makes repetition of experiment much easier. Polystyrene latex (PSL) spheres of diameter between 0.2 and $1.0{\mu}m$ are used. The present range of particle sizes is very important in controlling particle deposition on a wafer surface in industrial applications. For the present experiment, convection, diffusion, and sedimentation comprise important agents for deposition mechanisms. To investigate confidence interval of experimental data, mean and standard deviation of average deposition velocities are obtained from more than ten data set for each PSL sphere size. It is found that the distribution of mean of average deposition velocities from the measurement agrees well with the predictions of Liu and Ahn(1987) and Emi et al.(1989).

• 한국CDE학회논문집
• /
• 제19권3호
• /
• pp.214-223
• /
• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• 반도체디스플레이기술학회지
• /
• 제8권1호
• /
• pp.1-5
• /
• 2009

Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제18권8호
• /
• pp.2366-2380
• /
• 2024

In this study, a high-speed template matching system is proposed for wafer-vision alignment. The proposed system is designed to rapidly locate markers in semiconductor equipment used for wafer-vision alignment. We optimized and implemented a template-matching algorithm for the high-speed processing of high-resolution wafer images. Owing to the simplicity of wafer markers, we removed unnecessary components in the algorithm and designed the system using a field-programmable gate array (FPGA) to implement high-speed processing. The hardware blocks were designed using the Xilinx ZCU104 board, and the pyramid and matching blocks were designed using programmable logic for accelerated operations. To validate the proposed system, we established a verification environment using stage equipment commonly used in industrial settings and reference-software-based validation frameworks. The output results from the FPGA were transmitted to the wafer-alignment controller for system verification. The proposed system reduced the data-processing time by approximately 30% and achieved a level of accuracy in detecting wafer markers that was comparable to that achieved by reference software, with minimal deviation. This system can be used to increase precision and productivity during semiconductor manufacturing processes.

• 반도체디스플레이기술학회지
• /
• 제2권3호
• /
• pp.31-36
• /
• 2003

On this study, an E.E(End-Effector) for the 300 mm wafer transfer robot system is newly suggested. It is a mechanical type with $180^{\circ}$ rotating ranges and is composed of 3-point arms, two plate springs and single-axis DC motor controlled by microchip. To design, relationship between the gripping force and the wafer deformation is analyzed by FEM. By analytic results, the gripping force for 300 mm wafer is confirmed as 255~274 gf. From experimental results on gripping force, repeatable position accuracy and gripping cycle times in a wafer cleaning system, we confirmed that the suggested E.E was well designed to satisfiy on the required performance for 300 mm wafer transfer robot system.

• 제어로봇시스템학회논문지
• /
• 제6권6호
• /
• pp.486-491
• /
• 2000

The dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using neural network in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, five features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision, back-propagation neural network is adopted to classify the dicing process into normal and abnormal dicing, and normal and damaged blade. Experiments have been performed for GaAs semiconductor wafer in the case of normal/abnormal dicing and normal/damaged blade. Based upon observation of the experimental results, the proposed scheme shown has a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 6.5%.

• 산업경영시스템학회지
• /
• 제39권1호
• /
• pp.73-80
• /
• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• 산업기술연구
• /
• 제43권1호
• /
• pp.49-55
• /
• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• 대한산업공학회지
• /
• 제36권2호
• /
• pp.125-137
• /
• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• 한국공작기계학회논문집
• /
• 제18권1호
• /
• pp.1-12
• /
• 2009

Presently, the semiconductor industry has the chronic problem. In the semiconductor industry, it has the semiconductor wafer, a package, the optical filter cut by using the saw blade, the mold, a laser etc. The cutting technique has the difficulty due to the rising of the production cost by the wearing of mold, the poor quality problem due to generated heat at the moment of cutting procedure and curve cutting etc. The goal of this time of national research and development project is develop the apparatus for solving the problem that the existing cutting technique has. The technology is so called waterjet abrasive method. This technology will be mainly applied to cut a semiconductor package and a wafer. Two important things to be considered are ripple effect(in other words, the scale of a market) and simplicity of an application.