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http://dx.doi.org/10.7315/CADCAM.2014.214

Bottleneck Detection Framework Using Simulation in a Wafer FAB  

Yang, Karam (Department of Industrial Engineering, Ajou University)
Chung, Yongho (Department of Industrial Engineering, Ajou University)
Kim, Daewhan (Defense Agency for Technology and Quality)
Park, Sang Chul (Department of Industrial Engineering, Ajou University)
Publication Information
Korean Journal of Computational Design and Engineering / v.19, no.3, 2014 , pp. 214-223 More about this Journal
Abstract
This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.
Keywords
Bottleneck detection; Semiconductor; Simulation; Wafer FAB;
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Times Cited By KSCI : 1  (Citation Analysis)
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