• 제목/요약/키워드: Semiconductor package

검색결과 237건 처리시간 0.023초

8빔 압저항형 가속도센서의 자기진단 기능을 위한 IC칩 제조 (Fabrication of IC Chip for Self-Diagnostic Function of a Eight-Beam Piezoresistive Accelerometer.)

  • 박창현;전찬봉;강희석;김종집;이원태;심준환;김동권;이종현
    • 센서학회지
    • /
    • 제8권1호
    • /
    • pp.38-44
    • /
    • 1999
  • 본 논문에서는 8빔 압저항형 가속도센서에서 하나 이상의 빔이 파손되는 대부분의 경우에 대하여 에러신호를 검출할 수 있는 자기진단회로를 구현하고, 이를 PSPICE를 사용하여 시뮬레이션으로 그 기능을 확인하였다. 또한 현재 상용으로 나오는 KA 324 증폭기의 레이아웃을 사용하여 자기진단회로를 표준 바이폴라(bipolar)공정을 이용하여 IC칩으로 제조하고, 24핀 플라스틱 패키지 한 후 자기진단 특성을 조사하였다. 이때, 측정된 회로의 자기진단 특성을 시뮬레이션 결과와 비교하였다.

  • PDF

마스크 이미지를 이용한 반도체 패키지 스크래치 검출 연구 (A Study on Scratch Detection of Semiconductor Package using Mask Image)

  • 이태희;박구락;김동현
    • 한국융합학회논문지
    • /
    • 제8권11호
    • /
    • pp.43-48
    • /
    • 2017
  • 반도체는 산업 기술의 발전을 주도하고 있는 첨단기술로서 전자제품의 소형, 경량화 달성으로 전자산업 시장을 끌어가고 있는 상황이다. 특히 반도체 생산 공정은 정밀하고 복잡한 공정으로 이루어져 있어 효과적인 생산이 필요하며, 최근 불량 검출을 위하여 컴퓨터와 카메라를 융합한 비전 시스템이 활용되고 있고, 특수한 공정에 의하여 가공된 미세 패턴의 형상을 측정하기 위한 시스템의 수요가 급속하게 증대되고 있다. 본 논문에서는 반도체 패키지의 스크래치 결함을 검출하기 위하여 마스크 이미지를 이용한 비전 알고리즘을 제안한다. 제안 시스템을 통하여 반도체 패키지 생산 공정에 적용하면 생산관리를 원활하게 할 수 있고, 빠른 패키지의 불량 판정으로 생산의 효율성이 높아질 것으로 기대된다.

경화제 변화에 따른 WLP(Wafer Level Package)용 신규 Epoxy Resin System의 경화특성 (Cure Properties of Novel Epoxy Resin Systems for WLP (Wafer Level Package) According to the Change of Hardeners)

  • 김환건
    • 반도체디스플레이기술학회지
    • /
    • 제21권2호
    • /
    • pp.57-67
    • /
    • 2022
  • The curing characteristics of naphthalene type epoxy resin systems according to the change of curing agent were investigated to develop a new next-generation EMC(Epoxy Molding Compound) with excellent warpage characteristics, low thermal expansion, and excellent fluidity for WLP(Wafer Level Package). As epoxy resins, DGEBA, which are representative bisphenol type epoxy resins, NE-16, which are the base resins of naphthalene type epoxy resins, and NET-OH, NET-MA, and NET-Epoxy resins newly synthesized based on NE-16 were used. As a curing agent, DDM (Diamino Diphenyl Methane) and CBN resin with naphthalene moiety were used. The curing reaction characteristics of these epoxy resin systems with curing agents were analyzed through thermal analysis experiments. In terms of curing reaction mechanism, DGEBA and NET-OH resin systems follow the nth curing reaction mechanism, and NE-16, NET-MA and NET-Epoxy resin systems follow the autocatalytic curing reaction mechanism in the case of epoxy resin systems using DDM as curing agent. On the other hand, it was found that all of them showed the nth curing reaction mechanism in the case of epoxy resin systems using CBN as the curing agent. Comparing the curing reaction rate, the epoxy resin systems using CBN as the curing agent showed a faster curing reaction rate than them with DDM as a hardener in the case of DGEBA and NET-OH epoxy resin systems following the same nth curing reaction mechanism, and the epoxy resin systems with a different curing mechanism using CBN as a curing agent showed a faster curing reaction rate than DDM hardener systems except for the NE-16 epoxy resin system. These reasons were comparatively explained using the reaction rate parameters obtained through thermal analysis experiments. Based on these results, low thermal expansion, warpage reduction, and curing reaction rate in the epoxy resin systems can be improved by using CBN curing agent with a naphthalene moiety.

Reliability Issue in LOC Packages

  • Lee, Seong-Min
    • 한국재료학회:학술대회논문집
    • /
    • 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
    • /
    • pp.3-3
    • /
    • 1995
  • Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

  • PDF

전문가시스템 기법을 이용한 칩 캡슐화 성형설계 시스템

  • 허용정
    • 한국정밀공학회:학술대회논문집
    • /
    • 한국정밀공학회 1996년도 추계학술대회 논문집
    • /
    • pp.588-592
    • /
    • 1996
  • In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre-analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip Package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

  • PDF

반도체 회사의 인적 오류 예방 활동 사례 및 검토 (A Review on the Field Activities for the Human Error Prevention in a Semiconductor Company)

  • 이용희;이용희;류재승
    • 대한인간공학회지
    • /
    • 제30권1호
    • /
    • pp.117-125
    • /
    • 2011
  • While human error happens repeatedly in the semiconductor industry in Korea, which has brought a tremendous loss from manpower, welfare etc., there are limitations to human error prevention activities. When a semiconductor company introduces new machines and facilities from Japan or Germany, the companies often do not consider human factors in the design. Also, semiconductor companies are so occupied with promoting increased productivity, their attention to human errors has been pushed aside. Negative aspects of technical exchange associated with safety management are one aspect of the industry's nature. A semiconductor company recently began acknowledging on the back of TQM(Total Quality Management) that human error has a decisive effect on the safety. There are a number of uncontrollable and hard to handle event sets because the nature of these events with a human error may often be threatened or very intensive. It is strongly required that systemic studies should be performed to grasp the whole picture of a current situation for hazard factors. This study aims to examine the human error approach through the case of human error prevention field activities in a semiconductor industry compared with the activities and experience in nuclear power plants.

초음파 분량법에 의한 레진 내부 결합의 크기 측정에 관한 연구 (Sizing of lnner Flaw in Resin by using Ultrasonic spectroscopy)

  • Han, E.K.;Kim, Y.J.;Park, I.G.
    • 한국정밀공학회지
    • /
    • 제10권3호
    • /
    • pp.182-190
    • /
    • 1993
  • In manufacturing process of semiconductor package, the thermal stress owing to high temperature in moulding and the bubbles generated in chip bonding process become main causes to produce void. On this study we evaluated quantitatively void size by use of ultrasonic spectroscopy method which analyze the reflective pulses with broad band frequency in frequency domain, and after destructive testing we verified effectiv- eness of sizing void by use of ultasonic spectroscopy.

  • PDF

테이블의 변형을 최소화하는 스테이지 구조 설계

  • 정규원;박백한
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
    • /
    • pp.15-18
    • /
    • 2007
  • As the line width of the pattern become thin more and more, the accuracy of ultra-precision stage should be increased. Various type stages have been developed and used in fabrication phase and inspection lab. Furthermore the line with become several tens of nanometer recently. We need ultra high precision stage. In this paper a new type stage is proposed in order to reduce the deformation of working table. The table is supported by several flexure hinges and actuated by a PZT. The local deformation is analyzed and the vibratory motion is also examined by FEM package.

  • PDF

CSP의 Multi-sorting을 위한 pick and place 시스템의 개발 (The development of Pick and place system for multi-sorting of CSP)

  • 김찬용;곽철훈;이은상
    • 한국정밀공학회:학술대회논문집
    • /
    • 한국정밀공학회 1997년도 추계학술대회 논문집
    • /
    • pp.171-174
    • /
    • 1997
  • The great development of semiconductor industry demands the high efficiency and performance of related device, but the pick and place system of semiconductor packaging device can load a few units until nowdays. Although the system can load a lot of units, it can work multiple sort operation. The defect like that causes a low efficiency. Therefore, this paper represents the development of pick and place system which can work multiple sort operation.

  • PDF