• Title/Summary/Keyword: Semiconductor package

Search Result 236, Processing Time 0.03 seconds

A Study on the Defect Detection of Silicon-Chip Surrounding by Ultrasonic Wave - Automatic Determination Method of Threshold Value by Image Processing - (초음파를 이용할 실리콘 칩 주위의 결함 검출에 관한 연구 - 화상처리에 의한 threshold value의 자동 결정법 -)

  • 김재열;박환규
    • Proceedings of the Korean Society of Precision Engineering Conference
    • /
    • 1991.11a
    • /
    • pp.87-94
    • /
    • 1991
  • This Paper is to aim the microdefect evaluation of semiconductor Package into a quantitative from NDI's image processing of ultrasonic wave. Accordingly, for the detection of delamination between the Joining condition of boundary microdefect of semiconductor packaga the result from sampling original image, histogramming, binary image or image processing of multinumerloal value is such as the follows. ([) The least limitation from the microdefect detection of the semiconductor package by surveying high ultrasonic wave seems to be about 0.8 $\mu\textrm{m}$ in degree. (2) A result of applying the image processing of multinumerical value to the semiconductor package it was possible to devide the Category into the effectiveness.

  • PDF

Improvement of Temperature Characteristics in Ceramic-packaged Shunt Resistors (세라믹 패키지를 이용한 shunt 저항의 온도 특성 개선)

  • Kang, Doo-Won;Jo, Jungyol
    • Journal of the Semiconductor & Display Technology
    • /
    • v.14 no.3
    • /
    • pp.57-60
    • /
    • 2015
  • Electric power in large devices is controlled by digital circuits, such as switching mode power supply. This kind of power circuits require accurate current sensor for power distribution. We studied characteristics of shunt resistor, which has many advantages for commercial application compared to Hall-effect current sensor. We applied ceramic package to the shunt resistor. Ceramic package has good thermal conductivity compared to plastic package, and this point is important for space requirement in Printed Circuit Board (PCB). Another advantage of the ceramic package is that surface mount technology (SMT) can be used for production. Our experimental results showed that the ceramic packaged resistor showed about 50% lower temperature than the plastic packaged one. Burning point and frequency characteristics are also discussed.

Effect of Joule Heating on Electromigration Characteristics of Sn-3.5Ag Flip Chip Solder Bump (Joule열이 Sn-3.5Ag 플립칩 솔더범프의 Electromigration 거동에 미치는 영향)

  • Lee, Jang-Hee;Yang, Seung-Taek;Suh, Min-Suk;Chung, Qwan-Ho;Byun, Kwang-Yoo;Park, Young-Bae
    • Korean Journal of Materials Research
    • /
    • v.17 no.2
    • /
    • pp.91-95
    • /
    • 2007
  • Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

Electromigration and Thermomigration Characteristics in Flip Chip Sn-3.5Ag Solder Bump (플립칩 Sn-3.5Ag 솔더범프의 Electromigration과 Thermomigration 특성)

  • Lee, Jang-Hee;Lim, Gi-Tae;Yang, Seung-Taek;Suh, Min-Suk;Chung, Qwan-Ho;Byun, Kwang-Yoo;Park, Young-Bae
    • Korean Journal of Metals and Materials
    • /
    • v.46 no.5
    • /
    • pp.310-314
    • /
    • 2008
  • Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

BUMPLESS FLIP CHIP PACKAGE FOR COST/PERFORMANCE DRIVEN DEVICES

  • Lin, Charles W.C.;Chiang, Sam C.L.;Yang, T.K.Andrew
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • 2002.09a
    • /
    • pp.219-225
    • /
    • 2002
  • This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

  • PDF

A Study on the Inner Defect Inspection for Semiconductor Package by ESPI (ESPI를 이용한 반도체 패키지 내부결함 검사에 관한 연구)

  • Jung, Seung-Tack;Kim, Koung-Suk;Yang, Seung-Pil;Jung, Hyun-Chul;Lee, You-Hwang
    • Proceedings of the KSME Conference
    • /
    • 2003.11a
    • /
    • pp.1442-1447
    • /
    • 2003
  • Computer is a very powerful machine which is widely using for data processing, DB construction, peripheral device control, image processing etc. Consequently, many researches and developments have progressed for high performance processing unit, and other devices. Especially, the core units such as semiconductor parts are rapidly growing so that high-integration, high-performance, microminiat turization is possible. The packaging in the semiconductor industry is very important technique to de determine the performance of the system that the semiconductor is used. In this paper, the inspection of the inner defects such as delamination, void, crack, etc. in the semiconductor packages is studied. ESPI which is a non-contact, non-destructive, and full-field inspection method is used for the inner defect inspection and its results are compared with that of C-Scan method.

  • PDF

Semiconductor Backend Scheduling Using the Backward Pegging (Backward Pegging을 이용한 반도체 후공정 스케줄링)

  • Ahn, Euikoog;Seo, Jeongchul;Park, Sang Chul
    • Korean Journal of Computational Design and Engineering
    • /
    • v.19 no.4
    • /
    • pp.402-409
    • /
    • 2014
  • Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

Scheduling Methodology for MCP(Multi-chip Package) with Layer Sequence Constraint in Semiconductor Package (반도체 Package 공정에서 MCP(Multi-chip Package)의 Layer Sequence 제약을 고려한 스케쥴링 방법론)

  • Jeong, Young-Hyun;Cho, Kang-Hoon;Choung, You-In;Park, Sang-Chul
    • Journal of the Korea Society for Simulation
    • /
    • v.26 no.1
    • /
    • pp.69-75
    • /
    • 2017
  • An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

The Effect of Insulating Material on WLCSP Reliability with Various Solder Ball Layout (솔더볼 배치에 따른 절연층 재료가 WLCSP 신뢰성에 미치는 영향)

  • Kim, Jong-Hoon;Yang, Seung-Taek;Suh, Min-Suk;Chung, Qwan-Ho;Hong, Joon-Ki;Byun, Kwang-Yoo
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.13 no.4
    • /
    • pp.1-7
    • /
    • 2006
  • A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

  • PDF

On the 2D Vision Inspection Algorithm for Semiconductor Chip Package (반도체 패키지의 2차원 비전 검사 알고리즘에 관한 연구)

  • Yu, Sang-Hyun;Kim, Yong-Kwan
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.31 no.12C
    • /
    • pp.1157-1164
    • /
    • 2006
  • In this paper, we proposed a method for measuring accurate positions and sizes of package and balls in a micro BGA. To find defects of BGA accurately, we focused on finding positions of package and balls. After labeling, we detected connected components of package and balls using feature parameters. After the detection of package component, we measured position and size of package by employing rectangular model which was constructed by the package information. After the detection of the ball components, we measured positions and diameters of balls by employing circular models which were constructed by the ball informations. We did calibration based on landmarks to measure real length, and we compared the measured results with the SEM data. Finally, we found that the accuracy of the proposed method is 94% in terms of ball's radius.