• Title/Summary/Keyword: Semiconductor numerical simulation

검색결과 95건 처리시간 0.032초

다층 PCB 기판의 미세 가공을 위한 UV레이저 어블레이션에 관한 연구 (A Study on UV Laser Ablation for Micromachining of PCB Type Substrate)

  • 장원석;김재구;윤경구;신보성;최두선
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.887-890
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    • 1997
  • Recently micromachining using DPSSL(Diode Pumped Solid State Laser) with 3rd harmonic wavelength is actively studied in laser machining area. Micromachining using DPSSL have outstanding advantages as UV source comparing with excimer laser in various aspect such a maintenance cost, maskless machining, high repetition rate and so on. In this study micro-drilling of PCB type substrate which consists of Cu-PI-Cu layer was performed using DPSS Nd:YAG laser(355nm, wavelength) in vector scanning method. Experimental and numerical method(Matlab simulation, FEM) are used to optimize process parameter and control machining depth. The man mechanism of this process is laser ablation. It is known that there is large gap between energy threshold of copper and that of PI. Matlab simulation considering energy threshold of material is performed to effect of duplication of pulse and FEM thermal analysis is used to predict the ablation depth of copper. This study could be widely used in various laser micromachining including via hole microdrilling of PCB, and micromachining of semiconductor components, medical parts and printer nozzle and so on.

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인공신경망을 활용한 CMP 컨디셔닝 시스템 설계 변수에 따른 컨디셔닝 밀도의 불균일도 분석 (Nonuniformity of Conditioning Density According to CMP Conditioning System Design Variables Using Artificial Neural Network)

  • 박병훈;이현섭
    • Tribology and Lubricants
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    • 제38권4호
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    • pp.152-161
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    • 2022
  • Chemical mechanical planarization (CMP) is a technology that planarizes the surfaces of semiconductor devices using chemical reaction and mechanical material removal, and it is an essential process in manufacturing highly integrated semiconductors. In the CMP process, a conditioning process using a diamond conditioner is applied to remove by-products generated during processing and ensure the surface roughness of the CMP pad. In previous studies, prediction of pad wear by CMP conditioning has depended on numerical analysis studies based on mathematical simulation. In this study, using an artificial neural network, the ratio of conditioner coverage to the distance between centers in the conditioning system is input, and the average conditioning density, standard deviation, nonuniformity (NU), and conditioning density distribution are trained as targets. The result of training seems to predict the target data well, although the average conditioning density, standard deviation, and NU in the contact area of wafer and pad and all areas of the pad have some errors. In addition, in the case of NU, the prediction calculated from the training results of the average conditioning density and standard deviation can reduce the error of training compared with the results predicted through training. The results of training on the conditioning density profile generally follow the target data well, confirming that the shape of the conditioning density profile can be predicted.

Covered Microlens Structure for Quad Color Filter Array of CMOS Image Sensor

  • Jae-Hyeok Hwang;Yunkyung Kim
    • Current Optics and Photonics
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    • 제7권5호
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    • pp.485-495
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    • 2023
  • The pixel size in high-resolution complementary metal-oxide-semiconductor (CMOS) image sensors continues to shrink due to chip size limitations. However, the pixel pitch's miniaturization causes deterioration of optical performance. As one solution, a quad color filter (CF) array with pixel binning has been developed to enhance sensitivity. For high sensitivity, the microlens structure also needs to be optimized as the CF arrays change. In this paper, the covered microlens, which consist of four microlenses covered by one large microlens, are proposed for the quad CF array in the backside illumination pixel structure. To evaluate the optical performance, the suggested microlens structure was simulated from 0.5 ㎛ to 1.0 ㎛ pixels at the center and edge of the sensors. Moreover, all pixel structures were compared with and without in-pixel deep trench isolation (DTI), which works to distribute incident light uniformly into each photodiode. The suggested structure was evaluated with an optical simulation using the finite-difference time-domain method for numerical analysis of the optical characteristics. Compared to the conventional microlens, the suggested microlens show 29.1% and 33.9% maximum enhancement of sensitivity at the center and edge of the sensor, respectively. Therefore, the covered microlens demonstrated the highly sensitive image sensor with a quad CF array.

건식 식각 공정을 위한 초고속 병렬 연산 시뮬레이터 개발 (Development of High Performance Massively Parallel Processing Simulator for Semiconductor Etching Process)

  • 이제희;권오섭;반용찬;원태영
    • 전자공학회논문지D
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    • 제36D권10호
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    • pp.37-44
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    • 1999
  • 건식 식각 공정을 시뮬레이션하기 위하여, 플라즈마 챔버 내의 식각 이온 거동 메카니즘을 몬테카를로 수치해석 방식으로 구현하였고, 식각 이온의 거동에 의한 기판의 식각 형상을 확인하기 위하여 셀 방식의 표면 전진기를 개발하였다. 몬테카를로 수치 계산의 단점인 과다한 계산 시간을 효과적으로 감소시키기 위하여, CRAY T3E 병렬 컴퓨터와 여러대의 워크스테이션을 연결한 MPI 환경에서 몬테카를로 병렬 계산 알고리즘을 개발하였다. 본 연구에서 개발한 몬테카를로 병렬 계산 알고리즘은 95% 이상의 효율성을 보이며, 16개의 프로세서를 사용하였을 때 16의 스피드업(Speedup) 값을 얻었다. 또한 셀 방식의 병렬 연산 표면 전진기를 이용하여 토포그래피 시뮬레이션을 수행한 결과에서, 셀의 개수가 2갭만 개 일 때, 약 600Mb 이상의 메모리가 소요되므로 단일 워크스테이션 환경에서는 불가능한 계산이 본 연구에서 개발한 병렬 계산 알고리즘을 이용하였을 때 32개의 프로세서에서 15분의 계산시간이 소요되었다.

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Edge perturbation on electronic properties of boron nitride nanoribbons

  • K.L. Wong;K.W. Lai;M.W. Chuan;Y. Wong;A. Hamzah;S. Rusli;N.E. Alias;S. Mohamed Sultan;C.S. Lim;M.L.P. Tan
    • Advances in nano research
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    • 제15권5호
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    • pp.385-399
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    • 2023
  • Hexagonal boron nitride (h-BN), commonly referred to as Boron Nitride Nanoribbons (BNNRs), is an electrical insulator characterized by high thermal stability and a wide bandgap semiconductor property. This study delves into the electronic properties of two BNNR configurations: Armchair BNNRs (ABNNRs) and Zigzag BNNRs (ZBNNRs). Utilizing the nearest-neighbour tight-binding approach and numerical methods, the electronic properties of BNNRs were simulated. A simplifying assumption, the Hamiltonian matrix is used to compute the electronic properties by considering the self-interaction energy of a unit cell and the interaction energy between the unit cells. The edge perturbation is applied to the selected atoms of ABNNRs and ZBNNRs to simulate the electronic properties changes. This simulation work is done by generating a custom script using numerical computational methods in MATLAB software. When benchmarked against a reference study, our results aligned closely in terms of band structure and bandgap energy for ABNNRs. However, variations were observed in the peak values of the continuous curves for the local density of states. This discrepancy can be attributed to the use of numerical methods in our study, in contrast to the semi-analytical approach adopted in the reference work.

수치해석을 이용한 팬 아웃 웨이퍼 레벨 패키지의 휨 경향 및 신뢰성 연구 (Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package)

  • 이미경;정진욱;옥진영;좌성훈
    • 마이크로전자및패키징학회지
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    • 제21권1호
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    • pp.31-39
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    • 2014
  • 최근 모바일 응용 제품에 사용되는 반도체 패키지는 고밀도, 초소형 및 다기능을 요구하고 있다. 기존의 웨이퍼 레벨 패키지(wafer level package, WLP)는 fan-in 형태로, I/O 단자가 많은 칩에 사용하기에는 한계가 있다. 따라서 팬 아웃 웨이퍼 레벨 패키지(fan-out wafer level package, FOWLP)가 새로운 기술로 부각되고 있다. FOWLP에서 가장 심각한 문제 중의 하나는 휨(warpage)의 발생으로, 이는 FOWLP의 두께가 기존 패키지에 비하여 얇고, 다이 레벨 패키지 보다 휨의 크기가 매우 크기 때문이다. 휨의 발생은 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미친다. 본 연구에서는 FOWLP의 휨의 특성과 휨에 영향을 미치는 주요 인자에 대해서 수치해석을 이용하여 분석하였다. 휨을 최소화하기 위하여 여러 종류의 epoxy mold compound (EMC) 및 캐리어 재질을 사용하였을 경우에 대해서 휨의 크기를 비교하였다. 또한 FOWLP의 주요 공정인 EMC 몰딩 후, 그리고 캐리어 분리(detachment) 공정 후의 휨의 크기를 각각 해석하였다. 해석 결과, EMC 몰딩 후에 발생한 휨에 가장 영향을 미치는 인자는 EMC의 CTE이며, EMC의 CTE를 낮추거나 Tg(유리천이온도)를 높임으로서 휨을 감소시킬 수 있다. 캐리어 재질로는 Alloy42 재질이 가장 낮은 휨을 보였으며, 따라서 가격, 산화 문제, 열전달 문제를 고려하여 볼 때 Alloy 42 혹은 SUS 재질이 캐리어로서 적합할 것으로 판단된다.

나노구조 교환결합 삼층박막의 열적 안정성 예측 (Thermal Stability of a Nanostructured Exchange-coupled Trilayer)

  • 이종민;임상호
    • 한국자기학회지
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    • 제20권2호
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    • pp.75-82
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    • 2010
  • 나노구조 교환결합 삼층박막의 열적안정성을 예측하기 위한 최근의 연구진전에 대하여 리뷰한다. 새로운 해석적/수치적 방법을 이용하여 나노구조 교환결합 삼층박막의 에너지 배리어, 나아가서 열적안정성을 예측한다. 이 방법의 특징은 수치적인 방법을 이용하여 얻은 magnetostatic 자기장을 포함하는 해석적인 전체 에너지 방정식을 이용함에 있다. 단자구라는 가정하에, 모든 magnetostatic 자기장은 자성층 전체 부피에 대해 그 값을 평균함으로써 유효 값을 취할 수 있다. 그러나, 평형상태에서는 자구의 구조가 복잡하며, 또한 불안정한 saddle point에서의 자구 구조를 알 수 있는 직접적인 방법이 없기 때문에, saddle point에서의 magnetostatic 자기장 역시 얻을 수 없다. 이러한 어려움은 micromagnetic simulation을 통해 얻을 수 있는 critical 자기장과 saddle point에서의 magnetostatic 자기장을 연결하는 방정식을 사용함으로써 극복되었다. 이 방법은 신뢰성이 확보된 micromagnetic simulation에 기반을 두고 있기 때문에 열적안정성을 정확하게 예측하는 것이 가능하다.

저용량 가전용 40V급 Power MOSFET 소자의 설계 및 제작에 관한 연구 (A Design of 40V Power MOSFET for Low Power Electronic Appliances)

  • 강이구;안병섭;남태진;김범준;이용훈;정헌석
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.115-115
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    • 2009
  • Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The Power MOSFET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 40 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}\;cm^{-3}$, size of $600\;{\mu}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50\;{\mu}A$. We offer the layout of the proposed Power MOSFET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

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Experimental Investigations for Thermal Mutual Evaluation in Multi-Chip Modules

  • Ayadi, Moez;Bouguezzi, Sihem;Ghariani, Moez;Neji, Rafik
    • Journal of Power Electronics
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    • 제14권6호
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    • pp.1345-1356
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    • 2014
  • The thermal behavior of power modules is an important criterion for the design of cooling systems and optimum thermal structure of these modules. An important consideration for high power and high frequency design is the spacing between semiconductor devices, substrate structure and influence of the boundary condition in the case. This study focuses on the thermal behavior of hybrid power modules to establish a simplified method that allows temperature estimation in different module components without decapsulation. This study resulted in a correction of the junction temperature values estimated from the transient thermal impedance of each component operating alone. The corrections depend on mutual thermal coupling between different chips of the hybrid structure. A new experimental technique for thermal mutual evaluation is presented. Notably, the classic analysis of thermal phenomena in these structures, which was independent of dissipated power magnitude and boundary conditions in the case, is incorrect.

블랭킹 잔류응력에 의한 리드프레임 변형 수치해석을 위한 대격자 모델 (A Coarse Mesh Model for Numerical Analysis of Lead Frame Deformation Due to Blanking Residual Stress)

  • 김용연
    • 한국정밀공학회지
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    • 제22권2호
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    • pp.133-138
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    • 2005
  • The deformation of sheet metal due to the residual stress during blanking or piercing process, is numerically simulated by means of a commercial finite element code. Two dimensional plain strain problem is solved and then its result is applied to the deformation analysis of the lead frame. The plain strain element is applied to the 2D problem to observe the Von Mises equivalent stress concentration at the both shearing edges. As the punch penetrates into the sheet material, the stress concentration generated on both edges is getting increased to be the shearing surface. The limits of the punching depth applied to the simulation is 16% and 24% of the sheet thickness for the plain strain element and the hexahedral element, respectively. The hexahedral element and the limit of punching depth were applied to the deformation analysis of the lead frame for the blanking process. The FEM results for the lead deformation were very good agreement with the experimental ones. This paper shows that the coarse mesh has enabled to analyze the lead deformation generated due to the blanking mechanism. This simple approach to save the calculation time will be very effective to the design of the blanking tools in industries.