• Korean Journal of Materials Research
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• v.33 no.4
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• pp.142-150
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• 2023

AZO/Cu/AZO thin films were deposited on glass by RF magnetron sputtering. The specimens showed the preferred orientation of (0002) AZO and (111) Cu. The Cu crystal sizes increased from about 3.7 nm to about 8.5 nm with increasing Cu thickness, and from about 6.3 nm to about 9.5 nm with increasing heat treatment temperatures. The sizes of AZO crystals were almost independent of the Cu thickness, and increased slightly with heat treatment temperature. The residual stress of AZO after heat treatment also increased compressively from -4.6 GPa to -5.6 GPa with increasing heat treatment temperature. The increase in crystal size resulted from grain growth, and the increase in stress resulted from the decrease in defects that accompanied grain growth, and the thermal stress during cooling from heat treatment temperature to room temperature. From the PL spectra, the decrease in defects during heat treatment resulted in the increased intensity. The electrical resistivities of the 4 nm Cu film were 5.9×10^-4 Ω·cm and about 1.0×10^-4 Ω·cm for thicker Cu films. The resistivity decreased as the temperature of heat treatment increased. As the Cu thickness increased, an increase in carrier concentration resulted, as the fraction of AZO/Cu/AZO metal film increased. And the increase in carrier concentration with increasing heat treatment temperature might result from the diffusion of Cu ions into AZO. Transmittance decreased with increasing Cu thicknesses, and reached a maximum near the 500 nm wavelength after being heat treated at 200 ℃.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.504-508
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• 2022

Single crystal gallium oxide (Ga₂O₃) has been an emerging material for power semiconductor applications. However, the defect distribution of Ga₂O₃ substrates needs to be carefully characterized to improve crystal quality during crystal growth. We analyzed the type and the distribution of defects on commercial (-201) Ga₂O₃ substrates to get a basic standard prior to growing Ga₂O₃ crystals. Etch pit technique was employed to expose the type of defects on the Ga₂O₃ substrates. Synchrotron white beam X-ray topography was also utilized to observe the defect distribution by a nondestructive manner. We expect that the observation of defect distribution with three-dimensional geometry will also be useful for other crystal planes of Ga₂O₃ single crystals.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.74-80
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• 2023

Gallium oxide (Ga₂O₃) thin films were grown on c-, a-, m-, r-plane sapphire substrates using a mist chemical vapor deposition system. Various growth temperature range of 400~600℃ was applied for Ga₂O₃ thin film deposition. Then, several structural properties were characterized such as film thickness, crystal phase, lattice orientation, surface roughness, and optical bandgap. Under the certain growth temperature of 500℃, all grown Ga₂O₃ featured rhombohedral crystal structures and well-aligned preferred orientation to sapphire substrate. The films grown on c-and r-plane sapphire substrates, showed low surface roughness and large optical bandgap compared to those on a-and m-plane substrates. Therefore, various sapphire orientation can be potentially applicable for future Ga₂O₃-based electronics applications.

• Journal of the Korean institute of surface engineering
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• v.57 no.3
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• pp.165-178
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• 2024

In semiconductor memory device manufacturing, the capability for high aspect ratio contact (HARC) etching determines the density of memory device. Given that there is no standardized definition of "high" in high aspect ratio, it is crucial to continuously monitor recent technology trends to address technological gaps. Not only semiconductor memory manufacturing companies such as Samsung Electronics, SK Hynix, and Micron but also semiconductor manufacturing equipment companies such as Lam Research, Applied Materials, Tokyo Electron, and SEMES release annual reports on HARC etching technology. Although there is a gap in technological focus between semiconductor mass production environments and various research institutes, the results from these institutes significantly contribute by demonstrating fundamental mechanisms with empirical evidence, often in collaboration with industry researchers. This paper reviews recent studies on HARC etching and the study of dielectric etching in various technologies.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.72.2-72
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• 1998

• Korean Journal of Materials Research
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• v.3 no.2
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• pp.193-196
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• 1993

A procedure for preparing cross-sectional specimens for transmission electron microscopy(TEM)by focused ion beam(FIB)milling of specific regions of semiconductor devices is outlined. This technique enables TEM specimens to be pripared at precisely preselected area. In-situ #W thin film deposition on the top surface of desired site is complementally used to secure the TEM specimens to be less wedge shaped, which is main shortcoming of previous FIB-assisted TEM sample preparation technique. This technique is quite useful for the TEM sample priparation for fault finding and the characterization of fabrication process associated with submicron contact technologies.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.311-313
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• 2009

최근 심각한 환경오염 문제와 화석 에너지 고갈로 차세대 청정에너지 개발에 대한 중요성이 증대되고 있다. 그 중에서 태양전지는 공해가 적고, 자원이 무한적이며 반영구적인 수명을 가지고 있어 미래 에너지 문제를 해결할 수 있는 에너지원으로 기대되고 있다. 태양전지 기술 개발 방향은 발전 단가를 낮추는 태양전지 변환 효율 개선 연구위주로 연구가 진행되어 왔다. 태양전지의 변환 효율은 새로운 물질의 개발과 개선된 등으로 통하여 연구가 진행되어 왔다. 하지만, 태양전지를 개발하는데 있어서 많은 비용을 차지하는 것은 제조공정의 단순화가 우선일 것이다. 본 연구에서는 태양전지 제작하는 공정을 단순화 하고 그 공정 중에 생성되는 박막의 표면 분석에 대한 연구를 진행하였다. 낮추기 위하여 저가로 대량 생산이 가능하도록 다양한 물질과 공정이 개발되었지만, 변환 효율이 낮아 상용화에 큰 걸림돌이 되고 있다. 또한 변환 효율 향상을 위한 연구는 과거에는 변환 효율이 높은 물질을 찾기 위해 다양한 시도가 이루어졌으며, 현재는 물질 합성과 적층 구조 등을 이용하여 광흡수 대역을 넓혀 변환 효율을 높이는데 주력하고 있다.

• Korean Journal of Materials Research
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• v.19 no.5
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Current Applied Physics
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• v.18 no.12
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• pp.1558-1563
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• 2018

We demonstrate improved surface pit and phase separation in thick InGaN grown on a GaN/Si (111) substrate, using plasma-assisted molecular beam epitaxy with an indium modulation technique. The formation of surface pit and compositional inhomogeneity in the InGaN epilayer are investigated using atomic force microscopy, scanning electron microscopy and temperature-dependent photoluminescence. Indium elemental mapping directly reveals that poor compositional homogeneity occurs near the pits. The indium-modulation epitaxy of InGaN minimizes the surface indium segregation, leading to the reduction in pit density and size. The phase separation in InGaN with a higher pit density is significantly suppressed, suggesting that the pit formation and the phase separation are correlated. We propose an indium migration model for the correlation between surface pit and phase separation in InGaN.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.