• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1419-1421
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• 1995

Nickel micro-structures are fabricated by electroless plating which shows better uniformity. Positive resist AZ4562 of 7 um thickness is patterned with minimum width of 2 um on poly-silicon as for sacrificial layer. The growth rate of Ni electroless plating is 10um/h both for the seed layer of Pt and TiW. TiW is found to be more practical than Pt, since it is very difficult to remove Pt with negligible damage to Ni structures.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.59-60
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• 2013

슈퍼캐패시터(Super Capacitor) 또는 울트라 캐패시터(Ultra Capacitor) 등으로 불리우는 전기 이중층 캐패시터(EDLC, Electric Double Layer Capacitor)는 기존 콘덴서보다 월등한 용량 특성을 가지며, 전극과 전해질의 화학반응을 이용하던 이차전지들과 달리 주로 계면반응을 사용한 축전원리를 이용하여 높은 출력밀도와 충방전 효율, 무제한에 가까운 사이클 특성을 가지고 있다. 또한 전류변화에 안정적이어서 기존의 이차전지와는 달리 보호회로를 생략할 수 있기 때문에 단순한 회로 구성이 가능하고 전극활물질로서 탄소재를 사용하여 환경 친화적인 특성을 가진 차세대 에너지저장장치라고 할 수 있다. 특히 50만 사이클이라는 우수한 수명특성으로 인해 기존의 이차전지가 사용되기 어려운 다양한 분야에 적용이 늘어가고 있는 추세에 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.80-85
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• 2022

ZnO-based transparent conductive films have been widely studied to achieve high performance optoelectronic devices such as next generation flexible and transparent display systems. In order to achieve a transparent flexible ZnO-based device, a low temperature growth technique using a flexible polymer substrate is required. In this work, high quality flexible ZnO films were grown on colorless polyimide substrate using atomic layer deposition (ALD). Transparent ZnO films grown from 80 to 200℃ were fabricated with a metal-semiconductor-metal structure photodetectors (PDs). As the growth temperature of ZnO film increases, the photocurrent of UV PDs increases, while the sensitivity of that decreases. In addition, it is found that the response times of the PDs become shorter as the growth temperature increases. Based on these results, we suggest that high-quality ZnO film can be grown below 200℃ in an atomic layer deposition system, and can be applied to transparent and flexible UV PDs with very fast response time and high photocurrent.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.17-20
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• 2018

IGZO thin films were prepared on n-type Si substrates to research the interface characteristics between IGZO and substrate. After the annealing processes, the depletion layer was formed at the interface to make a Schottky contact owing to the electron-hall fair recombination. The carrier density was decreased by the effect of depletion layer and the hall mobility decreased during the deposition processes. But the annealing effect of depletion layer increased the hall mobility because of the increment of potential barrier and the extension of depletion layer. It was confirmed that it is useful to observe the depletion effect and Schottky contact's properties by complementary using the Hall measurement and I-V measurement.

• Journal of the Semiconductor & Display Technology
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• v.18 no.2
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• pp.29-31
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• 2019

The ZTO/p-Si thin film was produced and investigated for tunneling phenomena caused by the interface characteristics of the depletion layer. ZTO thin film was deposited and heat treated to produce barrier potentials by the depletion layer. The negative resistance characteristics were shown in the thin film of ZTO heat treated at $100^{\circ}C$, and the insulation properties were the best. Current decreased in the negative voltage direction by nonlinear show key characteristics, and current decreased in tunneling phenomenon by negative resistance in the positive voltage direction. Heat treated at $100^{\circ}C$, the ZTO thin film has increased barrier potential in the areas of the depletion layer and therefore the current has increased rapidly. The current has decreased again as we go beyond the depletion layer. Therefore, tunneling can be seen to make insulation better. In the ZTO thin film heat treated at $70^{\circ}C$ without tunneling, leakage current occurred as current increased at positive voltage. Therefore, tunneling effects by negative resistance were found to enhance insulation properties electrically.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.90.1-90
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• 1998

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.280-283
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of the Korea Society for Simulation
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• v.14 no.4
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• pp.55-68
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• 2005

The advancement in semiconductor technology is leading toward smaller critical dimension designs and larger wafer manufactures. Due to such phenomena, semiconductor industry is in need of an accurate control of the process. Photolithography is one of the key processes where the pattern of each layer is formed. In this process, precise superposition of the current layer to the previous layer is critical. Therefore overlay parameters of the semiconductor photolithography process is targeted for this research. The complex relationship among the input parameters and the output metrologies is difficult to understand and harder yet to model. Because of the superiority in modeling multi-nonlinear relationships, neural networks is used for the simulator modeling. For training the neural networks, conjugate gradient method is employed. An experiment is performed to evaluate the performance among the proposed neural network simulator, stepwise regression model, and the currently practiced prediction model from the test site.

• Journal of the Korean institute of surface engineering
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• v.57 no.3
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• pp.125-139
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• 2024

As the limits of semiconductor integration are approached, the challenges in semiconductor processes have intensified. And, for the production of semiconductors with dimensions under a few nanometers and to resolve the issues related to nanoscale device fabrication, research on atomic layer etching (ALE) technology has been conducted. The investigation related to ALE encompasses not only silicon and dielectric materials but also metallic materials. Particularly, there is an increasing need for ALE in next-generation metal materials that could replace copper in interconnect materials. This brief review will summarize the concept and methods of ALE and describe recent studies on potential next-generation metal replacements for copper, along with their ALE processes.