• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.35 no.4
• /
• pp.1-9
• /
• 2012

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined, and numerical experiments are conducted.

• Transactions on Electrical and Electronic Materials
• /
• v.3 no.3
• /
• pp.14-17
• /
• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• 한국전자현미경학회:학술대회논문집
• /
• 2001.11a
• /
• pp.18-22
• /
• 2001

A technique to characterize specific site of materials using a combination of a dedicated focused ion beam system(FIB), and Intermediate-voltage scanning transmission electron microscope(STEM) or transmission electron microscope(TEM) equipped with a scanning electron microscope(SEM) unit has been developed. The FIB system is used for preparation of electron transparent thin samples, while STEM or TEM is used for localization of a specific site to be milled in the FIB system. An FIB-STEM(TEM) compatible sample holder has been developed to facilitate thin sample preparation with high positional accuracy Positional accuracy of $0.1{\mu}m$ or better can be achieved by the technique. In addition, an FIB micro-sampling technique has been developed to extract a small sample directly from a bulk sample in a FIB system These newly developed techniques were applied for the analysis of specific failure in Si devices and also for characterization of a specific precipitate In a metal sample.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.41 no.1
• /
• pp.79-84
• /
• 2013

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a PWM-IC (pulse width modulation-integrated circuit) controller, a MOSFET (metal-oxide semiconductor field effect transistor), inductor, capacitor, etc. It is shown that the variation of threshold voltage and the offset voltage in the electrical characteristics of PWM-IC increase by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 4 heavy ions applied for SEL (Single Event Latch-up) make the PWM pulse unstable. Also, the output waveform for the given input in the DC/DC converter is observed by the simulation program with integrated circuit emphasis (SPICE). TID testing on PWM-IC is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the PWM operation is studied at SEL testing after implementation of the controller board.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.3
• /
• pp.661-669
• /
• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.3
• /
• pp.142-145
• /
• 2015

In this work, open stubs were fabricated on a polyether sulfone (PES) substrate, and their basic radio frequency (RF) characteristics were investigated for application to RF matching components of a flexible monolithic microwave integrated circuit (MMIC). According to the results, an open stub employing coplanar waveguide (OSCPW) on PES exhibited much lower loss than that on silicon substrate. The OSCPW with a length of $500{\mu}m$ on PES showed capacitance values of 0.031 ~ 0.044 pF from 0.5 to 50 GHz. For application to a relatively high-value capacitive matching, an open stub employing a fishbone-type transmission line (OSFTTL) was fabricated on PES, and its characteristics were investigated. The OSFTTL showed much higher capacitance values than the OSCPW due to the high effective permittivity value. Specifically, the OSFTTL on PES showed capacitance values of 0.066 ~ 0.24 pF from 0.5 to 50 GHz, which are higher than those for the open stub on silicon substrate. The above results indicate that the OSCPW and OSFTTL on PES can be effectively used for application to low/high-value capacitive matching components on microwave and millimeter wave flexible MMIC. To the best of the authors' knowledge, this work is the first report of the investigation of RF capacitive matching components on PES substrate.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.479-479
• /
• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Journal of the Semiconductor & Display Technology
• /
• v.2 no.4
• /
• pp.37-40
• /
• 2003

We have studied micro-machining technologies to fabricate parts and sensors used in the semiconductor equipment. The studies were based on the silicon integrated circuit processes, and composed of the anisotropic etching of single crystal silicon to fabricate a membrane structure for hot and cold junctions in the infrared absorber. KOH and TMAH were used as etching solutions for the anisotropic wet etching for membrane structure formation. The etching characteristic was observed for the each solution, and etching rate was measured depending upon the temperature and concentration of the etching solution. The different characteristics were observed according to pattern directions and etchant concentration. The pattern was made to incline $45^{\circ}$ on the primary flat, and optimum etching property was obtained in the case of 30 wt% and $90^{\circ}C$ of KOH etching solution for the formation of the membrane structure.

• The Journal of the Convergence on Culture Technology
• /
• v.4 no.3
• /
• pp.287-291
• /
• 2018

The CNTFET, which is attracting attention as a next-generation semiconductor device, can obtain ballistic or near-ballistic transport at a lower voltage than that of conventional MOSFETs by depositing CNTs between the source and drain of the device. In order to increase the performance of the CNTFET, a large number of CNTs must be deposited at a high density in the CNTFET. Thus, various manufacturing processes to increase the density of the CNTs have been developed. Recently, the Directional Shrinking Transfer Method was developed and showed that the current density of the CNTFET device could be increased up to 150 uA/um. So, this method enhances the possibility of implementing a CNTFET-based integrated circuit. In this paper, we will discuss how to evaluate the performance of the CNTFET device compared to a MOSFET at the circuit level when the CNTFET is fabricated by the Directional Shrinkage Transfer Method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.28-33
• /
• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.